Jump to content

User contributions for Phi2x

Results for Phi2x talk block log uploads logs
A user with 0 edits. Account created on 1 September 2026.

23:3223:32, 5 July 2024 diff hist −47 Gate Array →Register RMR2 (ASIC & Advanced ROM mapping)
23:3123:31, 5 July 2024 diff hist −94 Gate Array →Register RMR (Control Interrupt counter, ROM mapping and Graphics mode)
23:3023:30, 5 July 2024 diff hist −47 Gate Array →Summary
23:2923:29, 5 July 2024 diff hist −94 Gate Array →Summary
23:2823:28, 5 July 2024 diff hist −30 Gate Array →Controlling the Gate Array
23:2423:24, 5 July 2024 diff hist −78 8255 →PPI Port C
23:2323:23, 5 July 2024 diff hist −43 8255 →PPI Port B
23:2323:23, 5 July 2024 diff hist −39 8255 →PPI Port A
23:2223:22, 5 July 2024 diff hist −55 8255 →The 8255 in the CPC
23:1923:19, 5 July 2024 diff hist −58 I/O Port Summary →Memory Mapped I/O Ports
23:1823:18, 5 July 2024 diff hist −58 I/O Port Summary →I/O Port Summary
23:1623:16, 5 July 2024 diff hist −90 Default I/O Port Summary →Memory Mapped I/O Ports
23:1523:15, 5 July 2024 diff hist −58 Default I/O Port Summary →I/O Ports
23:1223:12, 5 July 2024 diff hist −9 CRTC →Internal Counters
23:1123:11, 5 July 2024 diff hist −40 CRTC →CRTC register differences
23:0823:08, 5 July 2024 diff hist −238 CRTC →CRTC register differences
23:0223:02, 5 July 2024 diff hist −44 CRTC →CRTC registers
23:0123:01, 5 July 2024 diff hist −36 CRTC →Addressing
23:0023:00, 5 July 2024 diff hist −36 CRTC →Programming
22:5922:59, 5 July 2024 diff hist −36 CRTC →Overview
22:5822:58, 5 July 2024 diff hist −39 ASIC →Vectored Interrupt
22:5522:55, 5 July 2024 diff hist +3 ASIC →Vectored Interrupt
22:5122:51, 5 July 2024 diff hist +104 ASIC →Vectored Interrupt
22:3822:38, 5 July 2024 diff hist +20 ASIC →Vectored Interrupt
22:3722:37, 5 July 2024 diff hist +41 ASIC →Vectored Interrupt
22:3522:35, 5 July 2024 diff hist +76 ASIC →Vectored Interrupt
22:3322:33, 5 July 2024 diff hist +9 ASIC →Vectored Interrupt
22:3022:30, 5 July 2024 diff hist +5 ASIC →Vectored Interrupt
22:2922:29, 5 July 2024 diff hist +197 ASIC →Vectored Interrupt
22:1922:19, 5 July 2024 diff hist −7 ASIC →Programmable Raster Interrupt
22:1722:17, 5 July 2024 diff hist +16 ASIC →DMA commands
22:1322:13, 5 July 2024 diff hist +10 ASIC →DMA commands
22:1122:11, 5 July 2024 diff hist +53 ASIC →DMA commands
22:0422:04, 5 July 2024 diff hist 0 ASIC No edit summary
21:5621:56, 5 July 2024 diff hist +135 Default I/O Port Summary →Memory Mapped I/O Ports
14:1714:17, 5 July 2024 diff hist −14 ASIC →Vectored Interrupt
14:0814:08, 5 July 2024 diff hist +458 ASIC No edit summary
13:4313:43, 5 July 2024 diff hist +57 ASIC →DMA commands
13:2813:28, 5 July 2024 diff hist +108 ASIC →DMA commands
12:5312:53, 5 July 2024 diff hist +312 ASIC →DMA commands
12:4712:47, 5 July 2024 diff hist +144 ASIC →DMA commands
12:3012:30, 5 July 2024 diff hist −39 ASIC →Programmable Raster Interrupt
12:2612:26, 5 July 2024 diff hist −8 ASIC →Soft Scroll
12:2412:24, 5 July 2024 diff hist −12 ASIC →Soft Scroll
12:2312:23, 5 July 2024 diff hist −12 ASIC No edit summary
12:1612:16, 5 July 2024 diff hist +1,321 ASIC No edit summary
11:4711:47, 5 July 2024 diff hist −3 ASIC →Split Screen
11:4311:43, 5 July 2024 diff hist −52 ASIC No edit summary
11:3711:37, 5 July 2024 diff hist +664 ASIC No edit summary
10:4410:44, 5 July 2024 diff hist +20 Gate Array →Interrupt management

Retrieved from "https://wiki.amstrad-cpc.net/wiki/Special:Contributions/Phi2x"