User contributions for Phi2x
5 July 2024
- 10:4210:42, 5 July 2024 diff hist +15 ASIC →Programmable Raster Interrupt
- 10:2010:20, 5 July 2024 diff hist −1 ASIC →Programmable Raster Interrupt
- 10:1710:17, 5 July 2024 diff hist −249 Gate Array →Interrupt management
- 10:1710:17, 5 July 2024 diff hist +704 ASIC No edit summary
- 07:5407:54, 5 July 2024 diff hist −1 ASIC →DMA commands
- 07:3207:32, 5 July 2024 diff hist +14 ASIC →Internal Links
- 07:0207:02, 5 July 2024 diff hist +336 ASIC →DMA commands
- 06:4306:43, 5 July 2024 diff hist −1 ASIC →Emulated chips
- 06:4206:42, 5 July 2024 diff hist −2 ASIC →DMA commands
- 06:4106:41, 5 July 2024 diff hist +1 ASIC →DMA commands
- 06:3906:39, 5 July 2024 diff hist 0 ASIC →DMA commands
- 06:3706:37, 5 July 2024 diff hist +48 ASIC No edit summary
- 06:3606:36, 5 July 2024 diff hist +1,375 ASIC No edit summary
- 05:2705:27, 5 July 2024 diff hist +105 Emulators →Amstrad Plus
- 05:0505:05, 5 July 2024 diff hist 0 Default I/O Port Summary →Memory Mapped I/O Ports
- 05:0005:00, 5 July 2024 diff hist +20 Default I/O Port Summary →Memory Mapped I/O Ports
- 04:5804:58, 5 July 2024 diff hist −36 Default I/O Port Summary →Memory Mapped I/O Ports
- 04:5504:55, 5 July 2024 diff hist −14 Default I/O Port Summary →Memory Mapped I/O Ports
- 03:5303:53, 5 July 2024 diff hist +217 Default I/O Port Summary →Memory Mapped I/O Ports
- 03:4203:42, 5 July 2024 diff hist +6 Default I/O Port Summary No edit summary
- 03:4103:41, 5 July 2024 diff hist +69 Default I/O Port Summary No edit summary
- 03:3903:39, 5 July 2024 diff hist +2 Default I/O Port Summary →Memory Mapped I/O Ports
- 03:3803:38, 5 July 2024 diff hist +168 Default I/O Port Summary →Memory Mapped I/O Ports
- 03:1903:19, 5 July 2024 diff hist 0 765 FDC No edit summary
- 03:1903:19, 5 July 2024 diff hist 0 765 FDC →Accessing the FDC 765
- 03:1803:18, 5 July 2024 diff hist 0 765 FDC →Motor On/Off Flipflop
- 03:1703:17, 5 July 2024 diff hist +7 765 FDC →FDC Status Registers
- 03:1003:10, 5 July 2024 diff hist 0 765 FDC →C, H, R, N values at result phase
- 03:1003:10, 5 July 2024 diff hist +1,268 765 FDC No edit summary
- 00:4800:48, 5 July 2024 diff hist 0 Gate Array →Interrupt management
4 July 2024
- 23:3923:39, 4 July 2024 diff hist −1 CRTC →R10/R11 on ASIC/Pre-ASIC
- 23:3923:39, 4 July 2024 diff hist +1 CRTC →CRTC register differences
- 23:3723:37, 4 July 2024 diff hist +72 CRTC →CRTC register differences
- 23:0923:09, 4 July 2024 diff hist 0 Video modes No edit summary current
- 23:0123:01, 4 July 2024 diff hist +31 ASIC →Internal Links
- 23:0023:00, 4 July 2024 diff hist +29 Gate Array →Registers
- 22:5422:54, 4 July 2024 diff hist +6 Upper ROM Bank Number →ASIC ROM numbering system
- 22:5322:53, 4 July 2024 diff hist +1 Upper ROM Bank Number →ASIC ROM numbering system
- 22:4722:47, 4 July 2024 diff hist +404 Upper ROM Bank Number →ASIC ROM numbering system
- 19:4219:42, 4 July 2024 diff hist +2 Video modes No edit summary
- 19:4119:41, 4 July 2024 diff hist +2 Gate Array →Register RMR (Control Interrupt counter, ROM mapping and Graphics mode)
- 19:3819:38, 4 July 2024 diff hist +29 Gate Array →Register RMR2 (ASIC & Advanced ROM mapping)
- 19:3019:30, 4 July 2024 diff hist −6 Gate Array →Register RMR2 (ASIC & Advanced ROM mapping)
- 19:2719:27, 4 July 2024 diff hist −6 Gate Array →Register RMR2 (ASIC & Advanced ROM mapping)
- 19:2519:25, 4 July 2024 diff hist −8 Gate Array →Register RMR2 (ASIC & Advanced ROM mapping)
- 19:2419:24, 4 July 2024 diff hist +8 Gate Array →Register RMR2 (ASIC & Advanced ROM mapping)
- 19:0319:03, 4 July 2024 diff hist 0 Gate Array →Palette sorted by Firmware Colour Numbers
- 19:0319:03, 4 July 2024 diff hist 0 Gate Array →Palette sorted by Hardware Colour Numbers
- 18:5618:56, 4 July 2024 diff hist +4 Gate Array →Intensities
- 18:5418:54, 4 July 2024 diff hist 0 Gate Array →Palette sorted by Firmware Colour Numbers