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User contributions for Freemac

Results for Freemac talk block log uploads logs
A user with 0 edits. Account created on 1 September 2026.

14:1414:14, 18 October 2017 diff hist +124 FPGAmstrad →Instruction timing : talk about r005.8.16c20
06:3106:31, 18 October 2017 diff hist +581 FPGAmstrad →Instruction timing : talk about r005.8.16c20
06:2606:26, 18 October 2017 diff hist +1,004 FPGAmstrad →Instruction timing : talk about r005.8.16c4

17:2917:29, 14 October 2017 diff hist +68 FPGAmstrad →TODO : an OSD option to enable scan-doubler
08:0608:06, 14 October 2017 diff hist +1 User:Freemac No edit summary current

18:3618:36, 13 October 2017 diff hist +18 FPGAmstrad →TODO : welcome VGA signal
18:3518:35, 13 October 2017 diff hist +2 FPGAmstrad →TODO : pause Z80 while OSD is displayed
18:3118:31, 13 October 2017 diff hist +47 FPGAmstrad →ROM and RAM extension

20:1520:15, 12 October 2017 diff hist +40 FPGAmstrad →TODO : a OSD option to enable scan-doubler
20:1520:15, 12 October 2017 diff hist +231 FPGAmstrad →DONE: A SCART output

18:5518:55, 11 October 2017 diff hist −2 FPGAmstrad →State machine
18:5318:53, 11 October 2017 diff hist +2 FPGAmstrad →go further with USB sniffer
18:5218:52, 11 October 2017 diff hist +2 FPGAmstrad →State machine
18:5118:51, 11 October 2017 diff hist −1 FPGAmstrad →State machine
18:3418:34, 11 October 2017 diff hist +220 FPGAmstrad →State machine
18:2818:28, 11 October 2017 diff hist +22 FPGAmstrad →State machine
18:2718:27, 11 October 2017 diff hist +4 FPGAmstrad →State machine
18:2618:26, 11 October 2017 diff hist +15 FPGAmstrad →State machine
18:2518:25, 11 October 2017 diff hist +1 FPGAmstrad →State machine
18:2318:23, 11 October 2017 diff hist +3 FPGAmstrad →State machine
18:2218:22, 11 October 2017 diff hist +764 FPGAmstrad →State machine
18:0118:01, 11 October 2017 diff hist 0 FPGAmstrad →Third schematic Z80+ROM+RAM+VGA
18:0118:01, 11 October 2017 diff hist +2 FPGAmstrad →Third schematic Z80+ROM+RAM+VGA
18:0018:00, 11 October 2017 diff hist +2 FPGAmstrad →Third schematic Z80+ROM+RAM+VGA
18:0018:00, 11 October 2017 diff hist +9 FPGAmstrad →Third schematic Z80+ROM+RAM+VGA
17:5817:58, 11 October 2017 diff hist 0 FPGAmstrad →Third schematic Z80+ROM+RAM+VGA
17:4517:45, 11 October 2017 diff hist +3 FPGAmstrad →Tests on real CPC (by DanyPPC)
17:4417:44, 11 October 2017 diff hist +1 FPGAmstrad →Tests on real CPC (by DanyPPC)
17:4417:44, 11 October 2017 diff hist +364 FPGAmstrad →Tests on real CPC (by DanyPPC)

16:3416:34, 2 October 2017 diff hist 0 FPGAmstrad →Tests on real CPC (by DanyPPC)
16:2816:28, 2 October 2017 diff hist +172 FPGAmstrad →Tests on real CPC (by DanyPPC)

19:4119:41, 1 October 2017 diff hist +65 FPGAmstrad →Tests on real CPC (by DanyPPC)
13:1213:12, 1 October 2017 diff hist +70 N File:FPGAmstrad plustest5 r005.8.16c6 part2.png WinAPE's Plus Test testbench result running on CoreAmstrad r005.8.16c6 current
13:1113:11, 1 October 2017 diff hist +70 N File:FPGAmstrad plustest5 r005.8.16c6 part1.png WinAPE's Plus Test testbench result running on CoreAmstrad r005.8.16c6 current
13:0913:09, 1 October 2017 diff hist +224 FPGAmstrad →Some bad instruction timing analysis
10:5010:50, 1 October 2017 diff hist +61 FPGAmstrad →Tests on real CPC (by DanyPPC)

10:5510:55, 27 September 2017 diff hist +554 FPGAmstrad →Instruction timing : talk about r005.8.16c4

16:1716:17, 25 September 2017 diff hist +1 FPGAmstrad →Some bad instruction timing analysis
16:1616:16, 25 September 2017 diff hist +61 N File:FPGAmstrad plustest5 r005.8.16c4 part2.png r005.8.16c4 WinAPE's plustest.dsk testbench 5 result - part 2 current
16:1616:16, 25 September 2017 diff hist +61 N File:FPGAmstrad plustest5 r005.8.16c4 part1.png r005.8.16c4 WinAPE's plustest.dsk testbench 5 result - part 1 current
16:1516:15, 25 September 2017 diff hist +225 FPGAmstrad →Some bad instruction timing analysis

12:3112:31, 24 September 2017 diff hist +484 FPGAmstrad →On MiST-board CoreAmstrad version

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