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== I/O Port Address ==
== I/O Port Address ==


The project is rather unclear about the recommended I/O address: The Decoder's CPC example source code uses Port F8F0h. However, the 8bit Input Port project (which is, among others, explicitely intended for use with the Decoder) does use Port F8Exh.
The recommended I/O address (used in the CPC example source code) is Port F8F0h (ie. shorten Link 1 on the [[Maplins 8bit Input Port]]).
 
  Bit7    Dotclock (probably derived from E.O.C.) (end of ADC conversion)
  Bit6    Sync (used as hsync) (the sample program doesn't seem to do any vsync handling?)
  Bit5-4  Unknown/unused
  Bit3-0  Luminance


The decoder outputs some control signals and an 8bit luminance signal. That data can't be squeezed through the 8bit input port, so some of the luminance bits are left unconnected (the CPC's color palette couldn't display them anyways).
The decoder outputs some control signals and an 8bit luminance signal. That data can't be squeezed through the 8bit input port, so some of the luminance bits are left unconnected (the CPC's color palette couldn't display them anyways).
== Source Code ==
Here is a commented version of the original sample code...
--- basic code ---
5 MEMORY 30000:MODE 2
10 LOAD"wefax1.obj"
20 INPUT "enter horizontal resolution 1-4";resh
30 IF resh>0 AND resh<5 THEN POKE <resmod>,resh ELSE CLS:GOTO 20
40 CALL <entryoint>
50 CALL <rerun>
60 GOTO 50
--- asm code ---
io_port equ 0F8F0h
temp    equ 40000
lum    equ 40001
xreg    equ 40002
yreg    equ 40004
hxreg  equ 40006
blkadd  equ 40008
  org  0A028h  ;=41000 decimal
entrypoint: 
  ld  a,00h
  ld  [hxreg+1],a
  call 0BC0Eh  ;SCR_SET_MODE
rerun:
  ld  hl,160-1
  ld  [xreg],hl
  ld  hl,200-1
  ld  [yreg],hl
  ld  ix,bytead+15              ;\
  ld  a,0fh    ;ink index      ;
  ld  [temp],a ;ink index      ;
colset:                        ;
  ld  a,[ix]  ;ink address    ;
  ld  b,a                      ; init ink 0..15
  ld  c,a                      ;
  ld  a,[temp] ;ink index      ;
  call 0BC32h  ;SCR_SET_INK    ;
  ld  hl,temp  ;ink index      ;
  dec  [hl]    ;ink index      ;
  jp  m,wtfrm  ;lop done        ;
  dec  ix      ;ink address    ;
  jp  colset  ;lop next        ;/
wtfrm:
  call 0BD19h  ;MC_WAIT_FLYBACK
  call 0BD19h  ;MC_WAIT_FLYBACK
loop1:                          ;--- y loop ---
  di
  ld  bc,io_port
line:                          ;\
  in  a,[bc]  ;[port]          ;
  bit  6,a      ;[port].bit6    ;
  jr  z,line                    ;/
enline:                        ;\
  in  a,[bc]  ;[port]          ;
  bit  6,a      ;[port].bit6    ;
  jr  nz,enline                ;/
  ld  d,0Ah                    ;\
delay:                          ; delay
  dec  d                        ;
  jr  nz,delay                  ;/
loop2:                          ;--- x loop ---
  di
resmod equ $+1                  ;\horizontal resolution
  ld  d,2  ;<-- MODIFIED (1..4) ;/
  ld  bc,io_port
smpl:                          ;\
  in  a,[bc]  ;[port]          ;
  bit  7,a      ;[port].bit7    ;
  jr  nz,smpl                  ;/
ensmpl:                        ;\
  in  a,[bc]  ;[port]          ;
  bit  7,a      ;[port].bit7    ;
  jr  z,ensmpl                  ;/
  dec  d
  jr  nz,smpl
getlum:
  in  a,[bc]  ;[port]          ;\
  and  a,0fh    ;[port].bit0-3  ;
  ld  [lum],a                  ;/
  rra                            ;\
  rr  b                        ;
  rra                            ;
  rr  b                        ;
  rra                            ;
  rr  c                        ;
  rra                            ;
  rr  b                        ;
  ld  d,0                      ;
  rlc  b                        ;
  rr  d                        ;
  rr  d                        ;
  rlc  b                        ;
  rr  d                        ;
  rr  d                        ;
  rlc  c                        ;
  rr  d                        ;
  rr  d                        ;
  rlc  b                        ;
  rr  d                        ;/
  ld  a,[xreg]
  rra
  jr  nc,nolft
  or  a    ;cy=0
  rr  d
nolft:
  ld  [hxreg],a
  ld  a,d      ;pixel value
  ld  [temp],a  ;pixel value
  ld  hl,5000h                  ;\
  ld  a,[yreg]                  ;
  srl  a    ;\                  ;
  srl  a    ;                    ;
  srl  a    ;/                  ;
  ld  e,a                      ;
  ld  d,0                      ;
  ld  b,8                      ;
mult:                          ;
  add  hl,hl                    ;
  jr  nc,noadd                  ;
  add  hl,de                    ;
noadd:                          ;
  djnz mult                      ;
  ld  [blkadd],hl              ;/
  ld  a,[yreg]                  ;\
  sla  a    ;\                  ;
  sla  a    ;                    ;
  sla  a    ;/                  ;
  and  a,38h                    ; calc vram address
  ld  h,a                      ;
  ld  l,0                      ;
  ld  bc,[blkadd]              ;
  add  hl,bc                    ;
  ld  bc,0c000h  ;vram base    ;
  add  hl,bc                    ;
  ld  hl,[hxreg]                ;
  add  hl,bc                    ;/
  ld  a,[temp]  ;pixel value  ;\
  ld  ix,xreg                  ;
  bit  0,[ix]                    ;
  jr  nz,plot                  ; draw pixel
  or  a,[hl]    ;merge pixels  ;
plot:                          ;
  ld  [hl],a                    ;/
  ld  bc,0001h                  ;\
  ld  hl,[xreg]                ;
  or  a    ;cy=0              ;
  sbc  hl,bc                    ; next x
  jr  c,nexy                    ;
  ld  [xreg],hl                ;
  jp  loop2                    ;/
nexy:                          ;\
  ld  hl,160-1                  ;
  ld  [xreg],hl                ;
  ld  hl,[yreg]                ;
  or  a    ;cy=0              ;
  sbc  hl,bc                    ; next y
  jr  nc,newlin                ;
  ei      ;frame done          ;
  ret      ;return to basic      ;
newlin:                        ;
  ld  [yreg],hl                ;
  jp  loop1                    ;/
bytead:  ;color palette (increasing luminance on green monitor)
  db 0,1,2,4, 5,6,8,10, 12,14,16,18, 20,22,24,26


== Scanned Articles ==
== Scanned Articles ==
Line 13: Line 188:
* Weather Satellite Receiving System – Part 1 - Receiver - project 18 (not yet scanned, does somebody have it on paper?)
* Weather Satellite Receiving System – Part 1 - Receiver - project 18 (not yet scanned, does somebody have it on paper?)
* [[Media:Maplins Weather Satellite Part 2 (Decoder) (Project Book 20).pdf|Weather Satellite Receiving System – Part 2 - Decoder - project 20.a]] (pdf)
* [[Media:Maplins Weather Satellite Part 2 (Decoder) (Project Book 20).pdf|Weather Satellite Receiving System – Part 2 - Decoder - project 20.a]] (pdf)
* [[Media:Maplins Amstrad 8bit Input Port (Project Book 20).pdf|Amstrad 8bit Input Port (for use, among others, with the Satellite Receiver) - project 20.b]] (pdf)
* [[Media:Maplins Amstrad 8bit Input Port (Project Book 20).pdf|Amstrad 8bit Input Port (for use, among others, with the Satellite Receiver) - project 20.b]] (pdf) (see [[Maplins 8bit Input Port|here]] for details and commented schematic)


Judging from their name, the following maplin projects may be also related:
Judging from their name, the following maplin projects may be also related:
Line 20: Line 195:
* Weather Satellite Down Converter – Part 2 - project 23 (not yet scanned, does somebody have it on paper?)
* Weather Satellite Down Converter – Part 2 - project 23 (not yet scanned, does somebody have it on paper?)
* Weather Satellite Prediction Table - project 24 (not yet scanned, does somebody have it on paper?)
* Weather Satellite Prediction Table - project 24 (not yet scanned, does somebody have it on paper?)
[[Category:Peripherals]]

Latest revision as of 11:44, 8 September 2014

Weather Satellite decoder from Maplin. Consists of at least three separate projects: The analogue Receiver, the analogue to digital Decoder, and the 8bit Input Port for connecting it to the CPC. The Decoder project contains source code for BBC B and for Amstrad CPC.

I/O Port Address

The recommended I/O address (used in the CPC example source code) is Port F8F0h (ie. shorten Link 1 on the Maplins 8bit Input Port).

 Bit7    Dotclock (probably derived from E.O.C.) (end of ADC conversion)
 Bit6    Sync (used as hsync) (the sample program doesn't seem to do any vsync handling?)
 Bit5-4  Unknown/unused
 Bit3-0  Luminance

The decoder outputs some control signals and an 8bit luminance signal. That data can't be squeezed through the 8bit input port, so some of the luminance bits are left unconnected (the CPC's color palette couldn't display them anyways).

Source Code

Here is a commented version of the original sample code...

--- basic code ---
5 MEMORY 30000:MODE 2
10 LOAD"wefax1.obj"
20 INPUT "enter horizontal resolution 1-4";resh
30 IF resh>0 AND resh<5 THEN POKE <resmod>,resh ELSE CLS:GOTO 20
40 CALL <entryoint>
50 CALL <rerun>
60 GOTO 50
--- asm code ---
io_port equ 0F8F0h
temp    equ 40000
lum     equ 40001
xreg    equ 40002
yreg    equ 40004
hxreg   equ 40006
blkadd  equ 40008
 org  0A028h  ;=41000 decimal
entrypoint:  
 ld   a,00h
 ld   [hxreg+1],a
 call 0BC0Eh  ;SCR_SET_MODE
rerun:
 ld   hl,160-1
 ld   [xreg],hl
 ld   hl,200-1
 ld   [yreg],hl
 ld   ix,bytead+15              ;\
 ld   a,0fh    ;ink index       ;
 ld   [temp],a ;ink index       ;
colset:                         ;
 ld   a,[ix]   ;ink address     ;
 ld   b,a                       ; init ink 0..15
 ld   c,a                       ;
 ld   a,[temp] ;ink index       ;
 call 0BC32h   ;SCR_SET_INK     ;
 ld   hl,temp  ;ink index       ;
 dec  [hl]     ;ink index       ;
 jp   m,wtfrm  ;lop done        ;
 dec  ix       ;ink address     ;
 jp   colset   ;lop next        ;/
wtfrm:
 call 0BD19h   ;MC_WAIT_FLYBACK
 call 0BD19h   ;MC_WAIT_FLYBACK
loop1:                          ;--- y loop ---
 di
 ld   bc,io_port
line:                           ;\
 in   a,[bc]   ;[port]          ;
 bit  6,a      ;[port].bit6     ;
 jr   z,line                    ;/
enline:                         ;\
 in   a,[bc]   ;[port]          ;
 bit  6,a      ;[port].bit6     ;
 jr   nz,enline                 ;/
 ld   d,0Ah                     ;\
delay:                          ; delay
 dec  d                         ;
 jr   nz,delay                  ;/
loop2:                          ;--- x loop ---
 di
resmod equ $+1                  ;\horizontal resolution
 ld   d,2  ;<-- MODIFIED (1..4) ;/
 ld   bc,io_port
smpl:                           ;\
 in   a,[bc]   ;[port]          ;
 bit  7,a      ;[port].bit7     ;
 jr   nz,smpl                   ;/
ensmpl:                         ;\
 in   a,[bc]   ;[port]          ;
 bit  7,a      ;[port].bit7     ;
 jr   z,ensmpl                  ;/
 dec  d
 jr   nz,smpl
getlum:
 in   a,[bc]   ;[port]          ;\
 and  a,0fh    ;[port].bit0-3   ;
 ld   [lum],a                   ;/
 rra                            ;\
 rr   b                         ;
 rra                            ;
 rr   b                         ;
 rra                            ;
 rr   c                         ;
 rra                            ;
 rr   b                         ;
 ld   d,0                       ;
 rlc  b                         ;
 rr   d                         ;
 rr   d                         ;
 rlc  b                         ;
 rr   d                         ;
 rr   d                         ;
 rlc  c                         ;
 rr   d                         ;
 rr   d                         ;
 rlc  b                         ;
 rr   d                         ;/
 ld   a,[xreg]
 rra
 jr   nc,nolft
 or   a    ;cy=0
 rr   d
nolft:
 ld   [hxreg],a
 ld   a,d       ;pixel value
 ld   [temp],a  ;pixel value
 ld   hl,5000h                  ;\
 ld   a,[yreg]                  ;
 srl  a    ;\                   ;
 srl  a    ;                    ;
 srl  a    ;/                   ;
 ld   e,a                       ;
 ld   d,0                       ;
 ld   b,8                       ;
mult:                           ;
 add  hl,hl                     ;
 jr   nc,noadd                  ;
 add  hl,de                     ;
noadd:                          ;
 djnz mult                      ;
 ld   [blkadd],hl               ;/
 ld   a,[yreg]                  ;\
 sla  a    ;\                   ;
 sla  a    ;                    ;
 sla  a    ;/                   ;
 and  a,38h                     ; calc vram address
 ld   h,a                       ;
 ld   l,0                       ;
 ld   bc,[blkadd]               ;
 add  hl,bc                     ;
 ld   bc,0c000h  ;vram base     ;
 add  hl,bc                     ;
 ld   hl,[hxreg]                ;
 add  hl,bc                     ;/
 ld   a,[temp]   ;pixel value   ;\
 ld   ix,xreg                   ;
 bit  0,[ix]                    ;
 jr   nz,plot                   ; draw pixel
 or   a,[hl]     ;merge pixels  ;
plot:                           ;
 ld   [hl],a                    ;/
 ld   bc,0001h                  ;\
 ld   hl,[xreg]                 ;
 or   a     ;cy=0               ;
 sbc  hl,bc                     ; next x
 jr   c,nexy                    ;
 ld   [xreg],hl                 ;
 jp   loop2                     ;/
nexy:                           ;\
 ld   hl,160-1                  ;
 ld   [xreg],hl                 ;
 ld   hl,[yreg]                 ;
 or   a     ;cy=0               ;
 sbc  hl,bc                     ; next y
 jr   nc,newlin                 ;
 ei       ;frame done           ;
 ret      ;return to basic      ;
newlin:                         ;
 ld   [yreg],hl                 ;
 jp   loop1                     ;/
bytead:  ;color palette (increasing luminance on green monitor)
 db 0,1,2,4, 5,6,8,10, 12,14,16,18, 20,22,24,26

Scanned Articles

The Weather Satellite receiver consists of three Maplin projects:

Judging from their name, the following maplin projects may be also related:

  • Weather Satellite Down Converter – Part 1 - project 22 (not yet scanned, does somebody have it on paper?)
  • Weather Satellite Down Converter – Part 2 - project 23 (not yet scanned, does somebody have it on paper?)
  • Weather Satellite Prediction Table - project 24 (not yet scanned, does somebody have it on paper?)