VHDL - Revision history

Arnoldemu at 10:50, 11 March 2018

2018-03-11T10:50:40Z

← Older revision		Revision as of 10:50, 11 March 2018
Line 83:		Line 83:

	VHDL-AMS is theorical, it is about using an analog version of VHDL not running in FPGA. But VHDL-AMS books does cover also VHDL (if an author of book does understand VHDL-AMS, sure he does understand VHDL perfectly.....)		VHDL-AMS is theorical, it is about using an analog version of VHDL not running in FPGA. But VHDL-AMS books does cover also VHDL (if an author of book does understand VHDL-AMS, sure he does understand VHDL perfectly.....)

			[[Category:Hardware]]

Dingo: Expanded; Ada explained (perhaps better to move it into an article of its own); CPLD; Standards

2017-03-09T03:52:58Z

Expanded; Ada explained (perhaps better to move it into an article of its own); CPLD; Standards

@@ Line 1: / Line 1: @@
-VHDL (very high-level description language)
+VHDL (very high-level hardware description language)
-This is an electronic language having electronic behaviour. You can implement what you want numerical electronic schematics (you can also draw then and translate then into VHDL)
+This is an electronic language having electronic behaviour. You can implement what you want numerical electronic schematics (you can also draw them and translate then into VHDL)
-Its syntax does look like ADA language. It differs from computer langage as its first instruction does generaly look like :
+Its syntax does looks like and is derived from the Ada language family. It differs from computer langage as its first instruction does generaly look like :
   if rising_edge(clock) then
    output_wire <= input_wire xor 1;
@@ Line 15: / Line 15: @@
   output_wire <= output_wire_mem;
-VHDL can be synthetised (compiled) into [[FPGA]] chip. Two families of [[FPGA]] chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...
+== Application ==
 VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug their components together using drawn schematics.
 IDE :
 * Xilinx webpack
@@ Line 30: / Line 78: @@
 ** [http://www.amedia-computer.com Amedia Computer] - fr
-Books :
+== Books ==
 * Conception de circuits en VHDL et VHDL-AMS / Principes et méthodologie / Collection POLYTECH / Cépaduès-éditions / D. HOUZET L. BARRANDON
 * VHDL-AMS / Applications et enjeux industiels / Cours et exercices corrigés / 2e et 3e cycles écoles d'ingénieurs/ DUNOD / Yannick Hervé
 VHDL-AMS is theorical, it is about using an analog version of VHDL not running in FPGA. But VHDL-AMS books does cover also VHDL (if an author of book does understand VHDL-AMS, sure he does understand VHDL perfectly.....)

Freemac at 14:35, 5 March 2017

2017-03-05T14:35:58Z

← Older revision		Revision as of 14:35, 5 March 2017
Line 10:		Line 10:
	All instructions are run at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.		All instructions are run at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.

	You can also have local registered ~~value~~, using affectation operator ":=", without delta-time (at once) :		You can also have local registered values, using affectation operator ":=", without delta-time (at once) :
	output_wire_mem := input_wire xor 1;		output_wire_mem := input_wire xor 1;
	output_wire_mem := output_wire_mem xor 1;		output_wire_mem := output_wire_mem xor 1;

Freemac at 14:34, 5 March 2017

2017-03-05T14:34:29Z

← Older revision		Revision as of 14:34, 5 March 2017
Line 8:		Line 8:
	end if;		end if;

	All ~~instruction~~ are ~~runs~~ at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.		All instructions are run at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.

	You can also have local registered value, using affectation operator ":=", without delta-time (at once) :		You can also have local registered value, using affectation operator ":=", without delta-time (at once) :

Freemac at 14:12, 5 March 2017

2017-03-05T14:12:52Z

← Older revision		Revision as of 14:12, 5 March 2017
Line 33:		Line 33:
	* Conception de circuits en VHDL et VHDL-AMS / Principes et méthodologie / Collection POLYTECH / Cépaduès-éditions / D. HOUZET L. BARRANDON		* Conception de circuits en VHDL et VHDL-AMS / Principes et méthodologie / Collection POLYTECH / Cépaduès-éditions / D. HOUZET L. BARRANDON
	* VHDL-AMS / Applications et enjeux industiels / Cours et exercices corrigés / 2e et 3e cycles écoles d'ingénieurs/ DUNOD / Yannick Hervé		* VHDL-AMS / Applications et enjeux industiels / Cours et exercices corrigés / 2e et 3e cycles écoles d'ingénieurs/ DUNOD / Yannick Hervé

			VHDL-AMS is theorical, it is about using an analog version of VHDL not running in FPGA. But VHDL-AMS books does cover also VHDL (if an author of book does understand VHDL-AMS, sure he does understand VHDL perfectly.....)

Freemac at 14:09, 5 March 2017

2017-03-05T14:09:22Z

← Older revision		Revision as of 14:09, 5 March 2017
Line 23:		Line 23:

	Development starter-kit :		Development starter-kit :
	* [http://store.digilentinc.com/ Diligent] (instructive)		* [http://store.digilentinc.com/ Diligent] (instructive - really nice for learning)
	* [http://www.lextronic.fr/ Lextronic] - fr		* [http://www.lextronic.fr/ Lextronic] - fr

Freemac at 14:07, 5 March 2017

2017-03-05T14:07:29Z

← Older revision		Revision as of 14:07, 5 March 2017
Line 23:		Line 23:

	Development starter-kit :		Development starter-kit :
	* [http://store.digilentinc.com/ Diligent]		* [http://store.digilentinc.com/ Diligent] (instructive)
	* [http://www.lextronic.fr/ Lextronic] - fr		* [http://www.lextronic.fr/ Lextronic] - fr

Freemac at 14:06, 5 March 2017

2017-03-05T14:06:52Z

← Older revision		Revision as of 14:06, 5 March 2017
Line 20:		Line 20:
	IDE :		IDE :
	* Xilinx webpack		* Xilinx webpack
	* Quartus web edition		* Quartus web edition (Altera)

	Development starter-kit :		Development starter-kit :

Freemac at 14:06, 5 March 2017

2017-03-05T14:06:10Z

← Older revision		Revision as of 14:06, 5 March 2017
Line 16:		Line 16:

	VHDL can be synthetised (compiled) into [[FPGA]] chip. Two families of [[FPGA]] chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...		VHDL can be synthetised (compiled) into [[FPGA]] chip. Two families of [[FPGA]] chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...
	VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug ~~them~~ components together using drawn schematics.		VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug their components together using drawn schematics.

	IDE :		IDE :

Freemac at 14:03, 5 March 2017

2017-03-05T14:03:30Z

← Older revision		Revision as of 14:03, 5 March 2017
Line 8:		Line 8:
	end if;		end if;

	All instruction are runs at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then ~~take~~ effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.		All instruction are runs at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.

	You can also have local registered value, using affectation operator ":=", without delta-time (at once) :		You can also have local registered value, using affectation operator ":=", without delta-time (at once) :