SYMBiFACE II:IDE registers - Revision history

Phi2x at 07:42, 1 April 2025

2025-04-01T07:42:29Z

@@ Line 30: / Line 30: @@
 |'''#FD0F''' || Status Register || Command Register
 |}
 == See also ==

Phi2x: /* See also */

2025-04-01T07:17:33Z

Phi2x: /* See also */

2025-04-01T07:11:59Z

HAL6128 at 08:52, 15 January 2018

2018-01-15T08:52:47Z

← Older revision		Revision as of 08:52, 15 January 2018
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	\|'''#FD0D''' \|\| Cylinder High for CHS or LBA bits 16-23 \|\| Cylinder High for CHS or LBA bits 16-23		\|'''#FD0D''' \|\| Cylinder High for CHS or LBA bits 16-23 \|\| Cylinder High for CHS or LBA bits 16-23
	\|-		\|-
	\|'''#FD0E''' \|\| Device/Head Register (Bit 6=0 CHS, Bit 6=0 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27) \|\| Device/Head Register (Bit 6=0 CHS, Bit 6=0 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27)		\|'''#FD0E''' \|\| Device/Head Register (Bit 6=0 CHS, Bit 6=1 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27) \|\| Device/Head Register (Bit 6=0 CHS, Bit 6=1 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27)
	\|-		\|-
	\|'''#FD0F''' \|\| Status Register \|\| Command Register		\|'''#FD0F''' \|\| Status Register \|\| Command Register

Arnoldemu at 18:25, 31 March 2017

2017-03-31T18:25:36Z

← Older revision		Revision as of 18:25, 31 March 2017
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	\|'''#FD0D''' \|\| Cylinder High for CHS or LBA bits 16-23 \|\| Cylinder High for CHS or LBA bits 16-23		\|'''#FD0D''' \|\| Cylinder High for CHS or LBA bits 16-23 \|\| Cylinder High for CHS or LBA bits 16-23
	\|-		\|-
	\|'''#FD0E''' \|\| Device/Head Register (Bit 6=0 CHS, Bit 6=0 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27) \|\| (Bit 6=0 CHS, Bit 6=0 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) ~~Device/Head Register~~ (Bits 3..0 Head for CHS or LBA bits 24-27)		\|'''#FD0E''' \|\| Device/Head Register (Bit 6=0 CHS, Bit 6=0 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27) \|\| Device/Head Register (Bit 6=0 CHS, Bit 6=0 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27)
	\|-		\|-
	\|'''#FD0F''' \|\| Status Register \|\| Command Register		\|'''#FD0F''' \|\| Status Register \|\| Command Register

Arnoldemu at 18:25, 31 March 2017

2017-03-31T18:25:10Z

← Older revision		Revision as of 18:25, 31 March 2017
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	\|'''#FD09''' \|\| Error Register \|\| Features Register/''(Write Precomp Reg.)''		\|'''#FD09''' \|\| Error Register \|\| Features Register/''(Write Precomp Reg.)''
	\|-		\|-
	\|'''#FD0A''' \|\| Sector Count \|\| Sector Count		\|'''#FD0A''' \|\| Sector Count (0=256) \|\| Sector Count (0=256)
	\|-		\|-
	\|'''#FD0B''' \|\| Sector Number (LBA bits 0-7) \|\| Sector Number (LBA bits 0-7)		\|'''#FD0B''' \|\| Sector Number for CHS or LBA bits 0-7 \|\| Sector Number for CHS or LBA bits 0-7
	\|-		\|-
	\|'''#FD0C''' \|\| Cylinder Low (LBA bits 8-15) \|\| Cylinder Low (LBA bits 8-15)		\|'''#FD0C''' \|\| Cylinder Low for CHS or LBA bits 8-15 \|\| Cylinder Low for CHS or LBA bits 8-15
	\|-		\|-
	\|'''#FD0D''' \|\| Cylinder High (LBA bits 16-23) \|\| Cylinder High (LBA bits 16-23)		\|'''#FD0D''' \|\| Cylinder High for CHS or LBA bits 16-23 \|\| Cylinder High for CHS or LBA bits 16-23
	\|-		\|-
	\|'''#FD0E''' \|\| Device/Head Register (LBA bits 24-27) \|\| Device/Head Register (LBA bits 24-27)		\|'''#FD0E''' \|\| Device/Head Register (Bit 6=0 CHS, Bit 6=0 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27) \|\| (Bit 6=0 CHS, Bit 6=0 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) Device/Head Register (Bits 3..0 Head for CHS or LBA bits 24-27)
	\|-		\|-
	\|'''#FD0F''' \|\| Status Register \|\| Command Register		\|'''#FD0F''' \|\| Status Register \|\| Command Register

Arnoldemu at 18:22, 31 March 2017

2017-03-31T18:22:16Z

← Older revision		Revision as of 18:22, 31 March 2017
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	\|'''#FD0A''' \|\| Sector Count \|\| Sector Count		\|'''#FD0A''' \|\| Sector Count \|\| Sector Count
	\|-		\|-
	\|'''#FD0B''' \|\| Sector Number \|\| Sector Number		\|'''#FD0B''' \|\| Sector Number (LBA bits 0-7) \|\| Sector Number (LBA bits 0-7)
	\|-		\|-
	\|'''#FD0C''' \|\| Cylinder Low \|\| Cylinder Low		\|'''#FD0C''' \|\| Cylinder Low (LBA bits 8-15) \|\| Cylinder Low (LBA bits 8-15)
	\|-		\|-
	\|'''#FD0D''' \|\| Cylinder High \|\| Cylinder High		\|'''#FD0D''' \|\| Cylinder High (LBA bits 16-23) \|\| Cylinder High (LBA bits 16-23)
	\|-		\|-
	\|'''#FD0E''' \|\| Device/Head Register \|\| Device/Head Register		\|'''#FD0E''' \|\| Device/Head Register (LBA bits 24-27) \|\| Device/Head Register (LBA bits 24-27)
	\|-		\|-
	\|'''#FD0F''' \|\| Status Register \|\| Command Register		\|'''#FD0F''' \|\| Status Register \|\| Command Register

Arnoldemu at 16:25, 20 February 2016

2016-02-20T16:25:26Z

← Older revision		Revision as of 16:25, 20 February 2016
Line 3:		Line 3:
	The I/O ports operate in a "pass-through" like mode where the registers directly reflect those of the connected ATA device.		The I/O ports operate in a "pass-through" like mode where the registers directly reflect those of the connected ATA device.

	The [[X-~~MASS~~]] is a more modern ATA/IDE device which is compatible with the Symbiface 2 IDE registers and uses the same I/O ports.		The [[X-Mass]] is a more modern ATA/IDE device which is compatible with the Symbiface 2 IDE registers and uses the same I/O ports.

	This is the documentation about the '''IDE registers''' of the [[SYMBiFACE II]] expansion card.		This is the documentation about the '''IDE registers''' of the [[SYMBiFACE II]] expansion card.

Arnoldemu at 16:24, 20 February 2016

2016-02-20T16:24:51Z

← Older revision		Revision as of 16:24, 20 February 2016
Line 1:		Line 1:
	The Symbiface 2 operates the IDE device in 16-bit data transfer mode. 16-bits of data is buffered at a time within the Symbiface 2 and read via the Data port ~~below~~ 8 bits at a time.		The Symbiface 2 operates the ATA/IDE device in 16-bit data transfer mode. 16-bits of data is buffered at a time within the Symbiface 2 and read/written via the Data port I/O address 8 bits at a time. The device was designed when devices didn't support ATA CFA command set and 8-bit PIO data transfer so this is why it buffers 16-bit of data. (16-bits is the "native" data transfer of an ATA device).

	The I/O ports operate in a "pass-through" like mode where the registers directly reflect those of the connected ATA device.		The I/O ports operate in a "pass-through" like mode where the registers directly reflect those of the connected ATA device.

			The [[X-MASS]] is a more modern ATA/IDE device which is compatible with the Symbiface 2 IDE registers and uses the same I/O ports.

	This is the documentation about the '''IDE registers''' of the [[SYMBiFACE II]] expansion card.		This is the documentation about the '''IDE registers''' of the [[SYMBiFACE II]] expansion card.

Arnoldemu at 16:21, 20 February 2016

2016-02-20T16:21:48Z

← Older revision		Revision as of 16:21, 20 February 2016
Line 1:		Line 1:
	The Symbiface 2 operates the IDE device in 16-bit data transfer mode. ~~The~~ 16-~~bit~~ data is buffered in the Symbiface 2 and read via the Data port below 8 bits at a time.		The Symbiface 2 operates the IDE device in 16-bit data transfer mode. 16-bits of data is buffered at a time within the Symbiface 2 and read via the Data port below 8 bits at a time.

			The I/O ports operate in a "pass-through" like mode where the registers directly reflect those of the connected ATA device.

	This is the documentation about the '''IDE registers''' of the [[SYMBiFACE II]] expansion card.		This is the documentation about the '''IDE registers''' of the [[SYMBiFACE II]] expansion card.

← Older revision		Revision as of 07:17, 1 April 2025
Line 35:		Line 35:
	* [[SYMBiFACE II:IDE routines\|Low level IDE routines]]		* [[SYMBiFACE II:IDE routines\|Low level IDE routines]]
	* [[Programming:SYMBiFACE_II\|SYMBiFACE II documentations]]		* [[Programming:SYMBiFACE_II\|SYMBiFACE II documentations]]
	* [https://hddguru.com/documentation/ Official ~~technical documentation from~~ ATA1 (1994) to ATA8 (2006)]		* [https://hddguru.com/documentation/ Official ATA1 (1994) to ATA8 (2006) specifications]
	[[Category:Programming]]		[[Category:Programming]]

← Older revision		Revision as of 07:11, 1 April 2025
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	* [[SYMBiFACE II:IDE routines\|Low level IDE routines]]		* [[SYMBiFACE II:IDE routines\|Low level IDE routines]]
	* [[Programming:SYMBiFACE_II\|SYMBiFACE II documentations]]		* [[Programming:SYMBiFACE_II\|SYMBiFACE II documentations]]
	* [~~http~~://~~www~~.~~t13.org~~/~~documents/UploadedDocuments/project/d1153r18-ATA-ATAPI-4.pdf ATA~~/~~IDE-specification~~]		* [https://hddguru.com/documentation/ Official technical documentation from ATA1 (1994) to ATA8 (2006)]
	[[Category:Programming]]		[[Category:Programming]]