Motorola 68000 - Revision history

Phi2x: /* Register File */

2025-05-13T19:05:58Z

← Older revision		Revision as of 19:05, 13 May 2025
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	\| A0 - A6 \|\| 32-bit \|\| Address Registers \|\| General-purpose registers primarily used as pointers or index registers for memory addressing. Can be used for some 16-bit/32-bit arithmetic (operations usually affect the full 32 bits). Word operations typically sign-extend to 32 bits.		\| A0 - A6 \|\| 32-bit \|\| Address Registers \|\| General-purpose registers primarily used as pointers or index registers for memory addressing. Can be used for some 16-bit/32-bit arithmetic (operations usually affect the full 32 bits). Word operations typically sign-extend to 32 bits.
	\|-		\|-
	\| A7 (SP/USP/SSP) \|\| 32-bit \|\| Stack Pointer \|\| Two physically separate registers exist: User Stack Pointer (USP) and Supervisor Stack Pointer (SSP). The processor uses the active one based on the S-bit (Supervisor state) in the Status Register. Used implicitly by stack operations (`PEA`, `LINK`, `UNLK`, `MOVE to/from -(An)/(An)+`), subroutine calls (`JSR`, `BSR`), returns (`RTS`, `RTR`), and exceptions.		\| A7 (SP/USP/SSP) \|\| 32-bit \|\| Stack Pointer \|\| Two physically separate registers exist: User Stack Pointer (USP) and Supervisor Stack Pointer (SSP). The processor uses the active one based on the S-bit (Supervisor state) in the Status Register.
			Used implicitly by stack operations (`PEA`, `LINK`, `UNLK`, `MOVE to/from -(An)/(An)+`), subroutine calls (`JSR`, `BSR`), returns (`RTS`, `RTR`), and exceptions.
	\|-		\|-
	\| PC (Program Counter) \|\| 32-bit \|\| Points to the address of the next instruction to be fetched. \|\| Although 32-bit internally, the original 68000 had a 24-bit address bus (16MB addressable space). Later variants (68010+) used more address lines. Modified by branches, jumps, calls, returns, exceptions.		\| PC (Program Counter) \|\| 32-bit \|\| Points to the address of the next instruction to be fetched. \|\| Although 32-bit internally, the original 68000 had a 24-bit address bus (16MB addressable space). Later variants (68010+) used more address lines. Modified by branches, jumps, calls, returns, exceptions.
	\|-		\|-
	\| SR (Status Register) \|\| 16-bit \|\| Holds processor status (Condition Codes) and system control bits. Divided into User Byte (CCR) and System Byte. <br/> '''User Byte (CCR - Condition Code Register, bits 0-7):''' <br/> * bit 0 - C (Carry) <br/> * bit 1 - V (Overflow) <br/> * bit 2 - Z (Zero) <br/> * bit 3 - N (Negative) <br/> * bit 4 - X (Extend) <br/> '''System Byte (bits 8-15):''' <br/> * bit 10,9,8 - I2, I1, I0 (Interrupt Mask) <br/> * bit 13 - S (Supervisor State) <br/> * bit 15 - T (Trace Mode) <br/> (Other bits reserved/unused in base 68000) \|\| User programs can typically only read/write the CCR (lower byte). System Byte modification requires Supervisor privileges. X flag used for multi-precision arithmetic. S bit determines User/Supervisor mode (and active A7). T bit enables single-step tracing. I bits control interrupt priority level.		\| SR (Status Register) \|\| 16-bit \|\| Holds processor status (Condition Codes) and system control bits. Divided into User Byte (CCR) and System Byte. <br/> '''User Byte (CCR - Condition Code Register, bits 0-7):''' <br/> * bit 0 - C (Carry) <br/> * bit 1 - V (Overflow) <br/> * bit 2 - Z (Zero) <br/> * bit 3 - N (Negative) <br/> * bit 4 - X (Extend) <br/> '''System Byte (bits 8-15):''' <br/> * bit 10,9,8 - I2, I1, I0 (Interrupt Mask) <br/> * bit 13 - S (Supervisor State) <br/> * bit 15 - T (Trace Mode) <br/> (Other bits reserved/unused in base 68000) \|\| User programs can typically only read/write the CCR (lower byte). System Byte modification requires Supervisor privileges.
			X flag used for multi-precision arithmetic. S bit determines User/Supervisor mode (and active A7). T bit enables single-step tracing. I bits control interrupt priority level.
	\|}		\|}

Phi2x at 13:01, 2 May 2025

2025-05-02T13:01:15Z

← Older revision		Revision as of 13:01, 2 May 2025
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			[[File:Motorola 68000 CPU.jpg\|thumb\|right\|68000 CPU in plastic, ceramic and PLCC versions]]

	The [[Motorola 68000]] (commonly abbreviated as 68k) is a landmark microprocessor introduced in 1979 by Motorola Semiconductor.		The [[Motorola 68000]] (commonly abbreviated as 68k) is a landmark microprocessor introduced in 1979 by Motorola Semiconductor.

Phi2x: /* Instruction Set */

2025-04-28T22:54:15Z

Instruction Set

← Older revision		Revision as of 22:54, 28 April 2025
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	* U: undefined		* U: undefined

	~~There are multiple~~ families of instructions ~~that~~ use the CCR~~: Bcc, DBcc, Scc~~. The following table lists all the possible conditions we can test:		Bcc, DBcc and Scc families of instructions make use of the CCR. The following table lists all the possible conditions we can test:

	{\| class="wikitable"		{\| class="wikitable"

Phi2x: /* Instruction Set */

2025-04-28T22:52:49Z

Instruction Set

← Older revision		Revision as of 22:52, 28 April 2025
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	* U: undefined		* U: undefined

	There are multiple families of instructions that use the CCR: Bcc, DBcc, Scc~~, and TRAPcc~~. The following table lists all the possible conditions we can test:		There are multiple families of instructions that use the CCR: Bcc, DBcc, Scc. The following table lists all the possible conditions we can test:

	{\| class="wikitable"		{\| class="wikitable"

Phi2x: /* Instruction Set */

2025-04-28T22:49:22Z

Instruction Set

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 * 1: set
 * U: undefined
 <br>

Phi2x: /* Instruction Set */

2025-04-27T16:45:12Z

Instruction Set

← Older revision		Revision as of 16:45, 27 April 2025
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	<br>		<br>

	== Instruction Set ==		= Instruction Set =

	The Motorola 68000 was renowned for its rich, orthogonal instruction set:		The Motorola 68000 was renowned for its rich, orthogonal instruction set:

Phi2x: /* Architecture */

2025-04-27T16:40:04Z

Architecture

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 | SR (Status Register) || 16-bit || Holds processor status (Condition Codes) and system control bits. Divided into User Byte (CCR) and System Byte. <br/> '''User Byte (CCR - Condition Code Register, bits 0-7):''' <br/> * bit 0 - C (Carry) <br/> * bit 1 - V (Overflow) <br/> * bit 2 - Z (Zero) <br/> * bit 3 - N (Negative) <br/> * bit 4 - X (Extend) <br/> '''System Byte (bits 8-15):''' <br/> * bit 10,9,8 - I2, I1, I0 (Interrupt Mask) <br/> * bit 13 - S (Supervisor State) <br/> * bit 15 - T (Trace Mode) <br/> (Other bits reserved/unused in base 68000) || User programs can typically only read/write the CCR (lower byte). System Byte modification requires Supervisor privileges. X flag used for multi-precision arithmetic. S bit determines User/Supervisor mode (and active A7). T bit enables single-step tracing. I bits control interrupt priority level.
 |}
 <br>

Phi2x: /* Register Structure */

2025-04-27T16:39:32Z

← Older revision		Revision as of 16:39, 27 April 2025
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	<br>		<br>

	== Register ~~Structure~~ ==		== Register File ==

	~~The 68000’s register file is one of its most celebrated features. It provides~~:		{\| class="wikitable" style="white-space: nowrap;"
	* Data Registers (~~D0–D7~~)~~: These are 32 bits wide and are used for general~~-~~purpose arithmetic and logical operations~~. ~~However~~, ~~when operating on byte~~ or word ~~data~~, ~~only the lower 8 or 16 bits are affected~~.		! Register !! Size !! Description !! Notes
	* Address Registers ~~(A0–A7): Also 32 bits wide, these~~ registers ~~are~~ used for ~~pointer operations and~~ addressing ~~modes~~. ~~A7 doubles as~~ the ~~stack pointer (SP~~).		\|-
	* Status Register (SR): ~~This 16‑bit register comprises an 8‑bit system byte~~ (~~accessible only in supervisor mode~~) and ~~an 8‑bit user byte known as the condition code register~~ (~~CCR~~).		\| D0 - D7 \|\| 32-bit \|\| Data Registers \|\| General-purpose registers for data manipulation (arithmetic, logic). Can be accessed as 8-bit (byte, `.B`), 16-bit (word, `.W`), or 32-bit (long word, `.L`). Not typically used directly for memory addressing.
	**The ~~CCR contains~~ the ~~standard flags—zero~~ (Z), ~~carry~~ (C), ~~overflow~~ (V), ~~negative~~ (N), and ~~extend~~ (X).		\|-
	**~~The~~ 3 ~~least significant bits~~ (bits 8, 9 ~~and 10~~) of the ~~Status register’s System~~ byte ~~form the interrupt mask~~. ~~The interrupt priorities are numbered from 1 to 7, with level 7 having the highest priority~~. ~~The level 7 interrupt is nonmaskable and thus cannot be disabled~~.		\| A0 - A6 \|\| 32-bit \|\| Address Registers \|\| General-purpose registers primarily used as pointers or index registers for memory addressing. Can be used for some 16-bit/32-bit arithmetic (operations usually affect the full 32 bits). Word operations typically sign-extend to 32 bits.
	**Bit 13 of the status register is the S ~~flag, which specifies whether the MC68000 is in supervisor mode or user~~ mode.		\|-
	**Bit 15 of the status register is the T ~~flag, which specifies whether the MC68000 is in trace mode~~. ~~After each instruction is executed in the trace mode, a trap is forced so that a debugging program can monitor the results of that instruction’s execution~~.		\| A7 (SP/USP/SSP) \|\| 32-bit \|\| Stack Pointer \|\| Two physically separate registers exist: User Stack Pointer (USP) and Supervisor Stack Pointer (SSP). The processor uses the active one based on the S-bit (Supervisor state) in the Status Register. Used implicitly by stack operations (`PEA`, `LINK`, `UNLK`, `MOVE to/from -(An)/(An)+`), subroutine calls (`JSR`, `BSR`), returns (`RTS`, `RTR`), and exceptions.
			\|-
			\| PC (Program Counter) \|\| 32-bit \|\| Points to the address of the next instruction to be fetched. \|\| Although 32-bit internally, the original 68000 had a 24-bit address bus (16MB addressable space). Later variants (68010+) used more address lines. Modified by branches, jumps, calls, returns, exceptions.
			\|-
			\| SR (Status Register) \|\| 16-bit \|\| Holds processor status (Condition Codes) and system control bits. Divided into User Byte (CCR) and System Byte. <br/> '''User Byte (CCR - Condition Code Register, bits 0-7):''' <br/> * bit 0 - C (Carry) <br/> * bit 1 - V (Overflow) <br/> * bit 2 - Z (Zero) <br/> * bit 3 - N (Negative) <br/> * bit 4 - X (Extend) <br/> '''System Byte (bits 8-15):''' <br/> * bit 10,9,8 - I2, I1, I0 (Interrupt Mask) <br/> * bit 13 - S (Supervisor State) <br/> * bit 15 - T (Trace Mode) <br/> (Other bits reserved/unused in base 68000) \|\| User programs can typically only read/write the CCR (lower byte). System Byte modification requires Supervisor privileges. X flag used for multi-precision arithmetic. S bit determines User/Supervisor mode (and active A7). T bit enables single-step tracing. I bits control interrupt priority level.
			\|}

	<br>		<br>

Phi2x: /* Instruction Set */

2025-04-27T16:08:09Z

Instruction Set

Show changes

Phi2x: /* Microcode */

2025-04-26T20:29:05Z

Microcode

← Older revision		Revision as of 20:29, 26 April 2025
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	The microcode is a series of pointers into assorted microsubroutines in the nanocode. The nanocode performs the actual routing and selecting of registers and functions, and directs results. Decoding of an instruction's op code generates starting addresses in the microcode for the type of operation and the addressing mode. [http://www.easy68k.com/paulrsm/doc/dpbm68k1.htm Source]		The microcode is a series of pointers into assorted microsubroutines in the nanocode. The nanocode performs the actual routing and selecting of registers and functions, and directs results. Decoding of an instruction's op code generates starting addresses in the microcode for the type of operation and the addressing mode. [http://www.easy68k.com/paulrsm/doc/dpbm68k1.htm Source]

	See: [https://gendev.spritesmind.net/forum/viewtopic.php?t=3023 Tech topic about a microcode-level 68000 core] [https://www.atari-forum.com/viewtopic.php?t=42568 New 68k core in mame]		See: [https://gendev.spritesmind.net/forum/viewtopic.php?t=3023 Tech topic about a microcode-level 68000 core] [https://www.atari-forum.com/viewtopic.php?t=42568 New 68k core in mame] [https://og.kervella.org/m68k/ Motorola 68000 microcode]

	<br>		<br>