Intel 8086 - Revision history

Phi2x: /* Links */

2025-05-12T21:06:30Z

Links

← Older revision		Revision as of 21:06, 12 May 2025
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	*[https://slideshare.net/slideshow/pindiagramdetailsof8086microprocessor/266134566 Pin diagram of 8086]		*[https://slideshare.net/slideshow/pindiagramdetailsof8086microprocessor/266134566 Pin diagram of 8086]
	*[https://github.com/SingleStepTests Tom Harte's SingleStepTests]		*[https://github.com/SingleStepTests Tom Harte's SingleStepTests]
			*[https://github.com/reenigne/reenigne/blob/master/8088/acid88/acid88.txt Acid88] A testsuite for cycle-exact 8088 PC/XT emulators

	<br>		<br>

Phi2x: /* Secret Instruction */

2025-05-11T12:22:26Z

Secret Instruction

← Older revision		Revision as of 12:22, 11 May 2025
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	== Secret Instruction ==		== Secret Instruction ==

	The secret instruction is SALC (Set AL register to Carry). Its opcode is 0xD6. Intel put this in all its x86 processors but didn't document it, using it as a trap. If a manufacturer cloned an Intel processor, the presence of the SALC instruction would prove that the clone stole Intel's microcode.		The secret instruction is SALC (Set AL register to Carry). Its opcode is 0xD6. This instruction sets the AL register to 0 if the carry flag is 0, and sets the AL register to FF if the carry flag is 1.

			Intel put this in all its x86 processors but didn't document it, using it as a trap. If a manufacturer cloned an Intel processor, the presence of the SALC instruction would prove that the clone stole Intel's microcode.

	Intel sued NEC for making 8086 clones, claiming that NEC ripped off Intel's microcode. NEC claimed they wrote their own microcode. NEC's chip didn't have the secret SALC instruction and Intel lost the case.		Intel sued NEC for making 8086 clones, claiming that NEC ripped off Intel's microcode. NEC claimed they wrote their own microcode. NEC's chip didn't have the secret SALC instruction and Intel lost the case.

Phi2x at 13:10, 2 May 2025

2025-05-02T13:10:12Z

← Older revision		Revision as of 13:10, 2 May 2025
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			[[File:Siemens 8086-2 PDIP.jpg\|thumb\|right\|Intel 8086 manufactured by Siemens for Amstrad PC1512]]

	The Intel 8086 is a landmark 16‑bit microprocessor introduced by Intel in 1978. It was the first in the x86 family and established many architectural conventions that continue to influence modern personal computing.		The Intel 8086 is a landmark 16‑bit microprocessor introduced by Intel in 1978. It was the first in the x86 family and established many architectural conventions that continue to influence modern personal computing.

Phi2x: /* Secret Instruction */

2025-04-28T23:12:00Z

Secret Instruction

← Older revision		Revision as of 23:12, 28 April 2025
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	== Secret Instruction ==		== Secret Instruction ==

	The secret instruction is SALC (Set AL register to Carry). Its opcode is 0xD6. Intel put this in all its x86 processors but didn't document it as a trap. If a manufacturer cloned an Intel processor, the presence of the SALC instruction would prove that the clone stole Intel's microcode.		The secret instruction is SALC (Set AL register to Carry). Its opcode is 0xD6. Intel put this in all its x86 processors but didn't document it, using it as a trap. If a manufacturer cloned an Intel processor, the presence of the SALC instruction would prove that the clone stole Intel's microcode.

	Intel sued NEC for making 8086 clones, claiming that NEC ripped off Intel's microcode. NEC claimed they wrote their own microcode. NEC's chip didn't have the secret SALC instruction and Intel lost the case.		Intel sued NEC for making 8086 clones, claiming that NEC ripped off Intel's microcode. NEC claimed they wrote their own microcode. NEC's chip didn't have the secret SALC instruction and Intel lost the case.

Phi2x: /* Instruction Set */

2025-04-28T23:07:22Z

Instruction Set

← Older revision		Revision as of 23:07, 28 April 2025
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	\| XOR \|\| Logical Exclusive OR \|\| Destination ⊕ Source → Destination \|\| 0 \|\| * \|\| * \|\| U \|\| * \|\| 0		\| XOR \|\| Logical Exclusive OR \|\| Destination ⊕ Source → Destination \|\| 0 \|\| * \|\| * \|\| U \|\| * \|\| 0
	\|}		\|}

			Note: Some instructions like LOOPE and LOOPZ are mnemonics for the same opcode. They are provided to match different programming contexts: LOOPE when thinking in terms of equality (e.g., a comparison was equal), LOOPZ when thinking in terms of zero (e.g., result was zero).

	== Secret Instruction ==		== Secret Instruction ==

Phi2x: /* Memory Segmentation */

2025-04-27T17:04:00Z

Memory Segmentation

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	In this scheme, the BIU forms memory addresses by shifting a 16‑bit segment register four bits to the left and then adding a 16‑bit offset. This results in a 20‑bit physical address.		In this scheme, the BIU forms memory addresses by shifting a 16‑bit segment register four bits to the left and then adding a 16‑bit offset. This results in a 20‑bit physical address.

	Although this model can be seen as complex, it allowed small programs (fitting within a ~~64‑KB~~ segment) to be loaded at a fixed offset, simplifying relocation in many cases.		Although this model can be seen as complex, it allowed small programs (fitting within a 64KB segment) to be loaded at a fixed offset, simplifying relocation in many cases.

	See: [https://www.righto.com/2023/07/8086-pins.html Reverse-engineering the 8086 processor's address and data pin circuits]		See: [https://www.righto.com/2023/07/8086-pins.html Reverse-engineering the 8086 processor's address and data pin circuits]

Phi2x at 17:02, 27 April 2025

2025-04-27T17:02:52Z

← Older revision		Revision as of 17:02, 27 April 2025
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	Reverse-engineering the: [https://www.righto.com/2023/03/8086-multiplication-microcode.html multiplication algorithm] [https://www.righto.com/2023/04/reverse-engineering-8086-divide-microcode.html division microcode] [https://www.righto.com/2023/04/8086-microcode-string-operations.html string operations] [https://www.righto.com/2023/01/reverse-engineering-conditional-jump.html conditional jumps] [https://www.righto.com/2023/03/8086-register-codes.html register codes] [https://www.righto.com/2023/02/8086-modrm-addressing.html ModR/M addressing microcode] [https://www.righto.com/2023/02/how-8086-processor-determines-length-of.html instructions length] [https://www.righto.com/2023/02/silicon-reverse-engineering-intel-8086.html flags circuitry] [https://www.righto.com/2023/02/8086-interrupt.html interrupt circuitry] [https://www.righto.com/2023/01/reverse-engineering-intel-8086.html HALT circuitry] [https://www.righto.com/2020/08/reverse-engineering-8086s.html ALU circuitry] in the Intel 8086 processor		Reverse-engineering the: [https://www.righto.com/2023/03/8086-multiplication-microcode.html multiplication algorithm] [https://www.righto.com/2023/04/reverse-engineering-8086-divide-microcode.html division microcode] [https://www.righto.com/2023/04/8086-microcode-string-operations.html string operations] [https://www.righto.com/2023/01/reverse-engineering-conditional-jump.html conditional jumps] [https://www.righto.com/2023/03/8086-register-codes.html register codes] [https://www.righto.com/2023/02/8086-modrm-addressing.html ModR/M addressing microcode] [https://www.righto.com/2023/02/how-8086-processor-determines-length-of.html instructions length] [https://www.righto.com/2023/02/silicon-reverse-engineering-intel-8086.html flags circuitry] [https://www.righto.com/2023/02/8086-interrupt.html interrupt circuitry] [https://www.righto.com/2023/01/reverse-engineering-intel-8086.html HALT circuitry] [https://www.righto.com/2020/08/reverse-engineering-8086s.html ALU circuitry] in the Intel 8086 processor

	== ~~Pipeline Design~~ ==		== Block Diagrams ==

	Internally, the 8086 features a 16‑bit Execution Unit (EU) that performs arithmetic, logic, and control functions, while simultaneously a separate Bus Interface Unit (BIU) handles all data transfers and external communications.		Internally, the 8086 features a 16‑bit Execution Unit (EU) that performs arithmetic, logic, and control functions, while simultaneously a separate Bus Interface Unit (BIU) handles all data transfers and external communications.
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	See: [https://www.righto.com/2023/01/the-8086-processors-microcode-pipeline.html The 8086 processor's microcode pipeline from die analysis] [https://www.righto.com/2024/03/8088-prefetch-circuitry.html Intel 8088 processor's instruction prefetch circuitry] [https://www.righto.com/2024/04/intel-8088-bus-state-machine.html Inside the Intel 8088 processor's bus interface state machine]		See: [https://www.righto.com/2023/01/the-8086-processors-microcode-pipeline.html The 8086 processor's microcode pipeline from die analysis] [https://www.righto.com/2024/03/8088-prefetch-circuitry.html Intel 8088 processor's instruction prefetch circuitry] [https://www.righto.com/2024/04/intel-8088-bus-state-machine.html Inside the Intel 8088 processor's bus interface state machine]

	~~== Block Diagrams ==~~

	[[File:Block-diagram-of-8086.jpg]]		[[File:Block-diagram-of-8086.jpg]]

Phi2x: /* Pipeline Design */

2025-04-27T17:01:37Z

Pipeline Design

← Older revision		Revision as of 17:01, 27 April 2025
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	== Pipeline Design ==		== Pipeline Design ==

	Internally, the 8086 features a 16‑bit ~~execution unit~~ (EU) that performs arithmetic, logic, and control functions, while simultaneously a separate ~~bus interface unit~~ (BIU) handles all data transfers and external communications.		Internally, the 8086 features a 16‑bit Execution Unit (EU) that performs arithmetic, logic, and control functions, while simultaneously a separate Bus Interface Unit (BIU) handles all data transfers and external communications.

	The BIU includes a 6‑byte prefetch queue (4-byte for 8088). The EU fetches instructions from the prefetch queue (not directly from memory). It has no direct connection to the external system bus, relying entirely on the BIU for data and instruction access.		The BIU includes a 6‑byte prefetch queue (4-byte for 8088). The EU fetches instructions from the prefetch queue (not directly from memory). It has no direct connection to the external system bus, relying entirely on the BIU for data and instruction access.

Phi2x: /* Instruction Set */

2025-04-27T16:55:40Z

Instruction Set

Show changes

Phi2x: /* Register Structure */

2025-04-27T16:26:58Z

← Older revision		Revision as of 16:26, 27 April 2025
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	See: [https://www.righto.com/2023/07/8086-pins.html Reverse-engineering the 8086 processor's address and data pin circuits]		See: [https://www.righto.com/2023/07/8086-pins.html Reverse-engineering the 8086 processor's address and data pin circuits]

	== Register ~~Structure~~ ==		== Register File ==

	~~The 8086 provides fourteen 16‑bit registers. Its register file includes~~:		{\| class="wikitable" style="white-space: nowrap;"
			! Register !! Size !! Description !! Notes
	*'''Data Registers:''' AX (~~accumulator~~), BX (base), CX (counter), and DX (~~data~~). ~~Each accessible~~ as ~~high~~ (AH, BH, CH, DH) and ~~low (AL, BL, CL,~~ DL~~) 8‑bit registers~~.		\|-
	*'''Pointer and Index Registers:''' SP (stack ~~pointer~~), BP (~~base pointer~~), SI (source index), ~~and~~ DI (destination ~~index~~) used for ~~addressing and data manipulation~~.		\| AX (Accumulator) \|\| 16-bit \|\| Primary register for arithmetic, logic, I/O. \|\| Can be accessed as two 8-bit registers: AH (High) and AL (Low). Often an implied operand.
	*'''~~Segment Registers~~:''' CS (~~code~~)~~, DS~~ (~~data~~)~~, SS~~ (~~stack~~)~~, and ES~~ (~~extra~~) ~~which define the memory segments for program code, data, and the stack.~~		\|-
	*'''~~Instruction Pointer and~~ Flags:''' ~~A 16‑bit instruction pointer~~ (IP) ~~and a 16‑bit status register~~ (~~Flags~~). ~~This register includes six status flags~~ (~~zero, carry, sign, overflow, parity, and auxiliary carry~~) to ~~indicate~~ the ~~outcomes~~ of ~~operations~~. ~~It also contains three control flags:~~ the ~~Direction Flag controls~~ the ~~direction in which string instructions act,~~ the ~~Interrupt Flag~~ to ~~enable/disable interrupts~~ and the ~~Trap Flag~~ for ~~single-step debugging~~.		\| BX (Base) \|\| 16-bit \|\| General-purpose, often used as a base pointer for memory addressing. \|\| Can be accessed as BH and BL. Only GP register usable as an offset in memory addressing (e.g., `[BX]`).
			\|-
			\| CX (Count) \|\| 16-bit \|\| General-purpose, often used as a loop counter (`LOOP` instruction) and for string operations (`REP` prefixes). \|\| Can be accessed as CH and CL.
			\|-
			\| DX (Data) \|\| 16-bit \|\| General-purpose, used for I/O port addressing (`IN`, `OUT`), and holds high word in 16x16 multiplication / 32/16 division. \|\| Can be accessed as DH and DL.
			\|-
			\| SP (Stack Pointer) \|\| 16-bit \|\| Points to the top of the current stack (offset within SS). \|\| Used implicitly by `PUSH`, `POP`, `CALL`, `RET`, interrupts.
			\|-
			\| BP (Base Pointer) \|\| 16-bit \|\| Points to data within the stack segment (offset within SS). \|\| Often used to access function parameters and local variables on the stack.
			\|-
			\| SI (Source Index) \|\| 16-bit \|\| Used as a source pointer offset (usually within DS) for string operations. Can be used as a general-purpose index register. \|\| Default segment is DS, can be overridden.
			\|-
			\| DI (Destination Index) \|\| 16-bit \|\| Used as a destination pointer offset (usually within ES) for string operations. Can be used as a general-purpose index register. \|\| Default segment is ES for string ops, can be overridden.
			\|-
			\| IP (Instruction Pointer) \|\| 16-bit \|\| Holds the offset address of the next instruction to be executed within the current Code Segment (CS). \|\| Analogous to Program Counter (PC). Cannot be directly manipulated by most instructions (modified by jumps, calls, etc.). Physical address = (CS * 16) + IP.
			\|-
			\| FLAGS \|\| 16-bit \|\| Contains status and control flags: <br/> '''Status Flags:''' <br/> * bit 0 - CF (Carry Flag) <br/> * bit 2 - PF (Parity Flag) <br/> * bit 4 - AF (Auxiliary Carry Flag) <br/> * bit 6 - ZF (Zero Flag) <br/> * bit 7 - SF (Sign Flag) <br/> * bit 11 - OF (Overflow Flag) <br/> '''Control Flags:''' <br/> * bit 8 - TF (Trap Flag) <br/> * bit 9 - IF (Interrupt Enable Flag) <br/> * bit 10 - DF (Direction Flag) <br/> (Other bits are undefined/reserved in 8086) \|\| AF used for BCD arithmetic. DF controls string op direction (inc/dec SI/DI). TF enables single-stepping. IF enables maskable interrupts.
			\|-
			\| CS (Code Segment) \|\| 16-bit \|\| Points to the base address of the current code segment. \|\| Used with IP to find the next instruction.
			\|-
			\| DS (Data Segment) \|\| 16-bit \|\| Points to the base address of the current data segment. \|\| Default segment for most data access.
			\|-
			\| SS (Stack Segment) \|\| 16-bit \|\| Points to the base address of the current stack segment. \|\| Used with SP and BP.
			\|-
			\| ES (Extra Segment) \|\| 16-bit \|\| Points to the base address of an extra data segment. \|\| Often used as the destination segment for string operations (with DI).
			\|}

	<br>		<br>