Intel 8080 - Revision history

Phi2x at 06:29, 2 May 2025

2025-05-02T06:29:45Z

← Older revision		Revision as of 06:29, 2 May 2025
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	[[File:Intel 8080 open-closed.jpg\|thumb\|right\|Intel 8080]]		[[File:Intel 8080 open-closed.jpg\|thumb\|right\|Intel 8080]]
			[[File:KL Intel C8008-1.jpg\|thumb\|right\|Intel 8008]]

	The '''Intel 8080''' is a seminal CPU introduced in 1974 that gave rise to the personal computer/home computer/microcomputer revolution.		The '''Intel 8080''' is a seminal CPU introduced in 1974 that gave rise to the personal computer/home computer/microcomputer revolution.

Phi2x at 06:27, 2 May 2025

2025-05-02T06:27:32Z

← Older revision		Revision as of 06:27, 2 May 2025
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			[[File:Intel 8080 open-closed.jpg\|thumb\|right\|Intel 8080]]

	The '''Intel 8080''' is a seminal CPU introduced in 1974 that gave rise to the personal computer/home computer/microcomputer revolution.		The '''Intel 8080''' is a seminal CPU introduced in 1974 that gave rise to the personal computer/home computer/microcomputer revolution.

Phi2x: /* Instruction Cycle */

2025-04-27T20:08:26Z

Instruction Cycle

← Older revision		Revision as of 20:08, 27 April 2025
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	\|}		\|}

	See this [[Media:Intel 8080 details.pdf\|Intel 8080 document]], containing a detailed breakdown of ~~machine~~ cycles and T-states.		See this [[Media:Intel 8080 details.pdf\|Intel 8080 document]], containing a detailed breakdown of M-cycles and T-states.

	<br>		<br>

Phi2x: /* Instruction Cycle */

2025-04-27T20:07:42Z

Instruction Cycle

← Older revision		Revision as of 20:07, 27 April 2025
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	A full instruction cycle requires anywhere from 4 to 18 states for its completion, depending on the kind of instruction involved.		A full instruction cycle requires anywhere from 4 to 18 states for its completion, depending on the kind of instruction involved.

			{\| class="wikitable"
			\|+ T-state Definitions
			\|-
			! T-state !! Description
			\|-
			\| T1
			\| A memory address or I/O device number is placed on the Address Bus (A<sub>15-0</sub>); status information is placed on Data Bus (D<sub>7-0</sub>).
			\|-
			\| T2
			\| The CPU samples the READY and HOLD inputs and checks for halt instruction.
			\|-
			\| TW (optional)
			\| Processor enters wait state if READY is low or if HALT instruction has been executed.
			\|-
			\| T3
			\| An instruction byte (FETCH machine cycle), data byte (MEMORY READ, STACK READ) or interrupt instruction (INTERRUPT machine cycle) is input to the CPU from the Data Bus; or a data byte (MEMORY WRITE, STACK WRITE or OUTPUT machine cycle) is output onto the data bus.
			\|-
			\| T4, T5 (optional)
			\| States T4 and T5 are available if the execution of a particular instruction requires them; if not, the CPU may skip one or both of them. T4 and T5 are only used for internal processor operations.
			\|}

	See this [[Media:Intel 8080 details.pdf\|Intel 8080 document]], containing a detailed breakdown of machine cycles and T-states.		See this [[Media:Intel 8080 details.pdf\|Intel 8080 document]], containing a detailed breakdown of machine cycles and T-states.

Phi2x: /* History */

2025-04-27T19:16:57Z

History

← Older revision		Revision as of 19:16, 27 April 2025
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	==History==		==History==

	The 8080 is often said to be the "first truly usable microprocessor". This CPU ~~was~~ 10 times faster than its predecessor, the [[Intel 8008]] issued in 1972.		The 8080 is often said to be the "first truly usable microprocessor". This CPU is 10 times faster than its predecessor, the [[Intel 8008]] issued in 1972.

	The 8008 had, among other limitations, a rigid seven-level address call stack instead of a flexible Stack Pointer. The 8008 instruction set was itself based on the CPU board, built out of dozens of TTL chips, of the Datapoint 2200 computer. [https://www.righto.com/2023/08/datapoint-to-8086.html Source]		The 8008 had, among other limitations, a rigid seven-level address call stack instead of a flexible Stack Pointer. The 8008 instruction set was itself based on the CPU board, built out of dozens of TTL chips, of the Datapoint 2200 computer. [https://www.righto.com/2023/08/datapoint-to-8086.html Source]

Phi2x: /* Register File */

2025-04-27T18:49:46Z

← Older revision		Revision as of 18:49, 27 April 2025
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	* bit1 - 1 (Fixed)		* bit1 - 1 (Fixed)
	* bit0 - CF - Carry Flag		* bit0 - CF - Carry Flag
	\|\| AC is used for BCD arithmetic (DAA instruction).		\|\| HF is used for BCD arithmetic (DAA instruction).
	The accumulator and the flags together are called the PSW, or program status word.		The accumulator and the flags together are called the PSW, or program status word.

Phi2x: /* History */

2025-04-27T18:36:36Z

History

← Older revision		Revision as of 18:36, 27 April 2025
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	==History==		==History==

	The 8080 is often said to be the "first truly usable microprocessor".		The 8080 is often said to be the "first truly usable microprocessor". This CPU was 10 times faster than its predecessor, the [[Intel 8008]] issued in 1972.

	~~Its predecessor was the first 8-bit microprocessor, the [[Intel~~ 8008~~]]. It~~ had, among other limitations, a rigid seven-level address call stack instead of a flexible Stack Pointer. The 8008 instruction set was itself based on the CPU board, built out of dozens of TTL chips, of the Datapoint 2200 computer. [https://www.righto.com/2023/08/datapoint-to-8086.html Source]		The 8008 had, among other limitations, a rigid seven-level address call stack instead of a flexible Stack Pointer. The 8008 instruction set was itself based on the CPU board, built out of dozens of TTL chips, of the Datapoint 2200 computer. [https://www.righto.com/2023/08/datapoint-to-8086.html Source]

	Despite what their naming suggest, the Intel 8008 and [[Intel 4004]] were separate projects with distinct architectures and purposes. The 8008 was not an upgrade or evolution of the 4004. The die shot of the 4004 reveals the initials FF of the chip designer, Federico Faggin. The die shot of the 8008 reveals the initials HF of the chip designer, Hal Feeney.		Despite what their naming suggest, the Intel 8008 and [[Intel 4004]] were separate projects with distinct architectures and purposes. The 8008 was not an upgrade or evolution of the 4004. The die shot of the 4004 reveals the initials FF of the chip designer, Federico Faggin. The die shot of the 8008 reveals the initials HF of the chip designer, Hal Feeney.

Phi2x: /* Register File */

2025-04-27T18:21:26Z

← Older revision		Revision as of 18:21, 27 April 2025
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	* bit1 - 1 (Fixed)		* bit1 - 1 (Fixed)
	* bit0 - CF - Carry Flag		* bit0 - CF - Carry Flag
	\|\| AC is used for BCD arithmetic (DAA instruction). ~~Often paired with A as~~ the ~~16-bit Program Status Word (~~PSW).		\|\| AC is used for BCD arithmetic (DAA instruction).
			The accumulator and the flags together are called the PSW, or program status word.

			PSW can be pushed to or popped from the stack.
	\|-		\|-
	\| SP (Stack Pointer) \|\| 16-bit \|\| Points to the top of the stack \|\| Used for PUSH, POP, CALL, RET instructions		\| SP (Stack Pointer) \|\| 16-bit \|\| Points to the top of the stack \|\| Used for PUSH, POP, CALL, RET instructions

Phi2x: /* Instruction Cycle */

2025-04-27T18:11:35Z

Instruction Cycle

← Older revision		Revision as of 18:11, 27 April 2025
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	A full instruction cycle requires anywhere from 4 to 18 states for its completion, depending on the kind of instruction involved.		A full instruction cycle requires anywhere from 4 to 18 states for its completion, depending on the kind of instruction involved.

	See this [[Media:Intel 8080 details.pdf\|Intel 8080 ~~doc~~]], containing a detailed breakdown of machine cycles and T-states.		See this [[Media:Intel 8080 details.pdf\|Intel 8080 document]], containing a detailed breakdown of machine cycles and T-states.

	<br>		<br>

Phi2x: /* Instruction Cycle */

2025-04-27T18:09:42Z

Instruction Cycle

← Older revision		Revision as of 18:09, 27 April 2025
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	A full instruction cycle requires anywhere from 4 to 18 states for its completion, depending on the kind of instruction involved.		A full instruction cycle requires anywhere from 4 to 18 states for its completion, depending on the kind of instruction involved.

	See this [[Media:Intel 8080 details.pdf\|8080 doc]], containing a detailed breakdown of machine cycles and T-states.		See this [[Media:Intel 8080 details.pdf\|Intel 8080 doc]], containing a detailed breakdown of machine cycles and T-states.

	<br>		<br>