I/O Port Summary - Revision history

Phi2x: /* I/O Port Summary */

2025-04-11T01:40:11Z

I/O Port Summary

← Older revision		Revision as of 01:40, 11 April 2025
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	\|-		\|-
	\|-		\|-
	\|#~~F8F2~~\|\|?\|\|[[EMR MIDI Interface]]\|\|Read\|\|Write		\|#F8F3\|\|?\|\|[[EMR MIDI Interface]]\|\|Read\|\|Write
	\|-		\|-
	\|#F8F4\|\|?\|\|[[Music Machine]] ADC Read\|\|Read\|\| -		\|#F8F4\|\|?\|\|[[Music Machine]] ADC Read\|\|Read\|\| -

Phi2x: /* I/O Port Summary */

2025-01-10T15:15:30Z

I/O Port Summary

← Older revision		Revision as of 15:15, 10 January 2025
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	\|#FE82\|\|%11111110 10000010\|\|[[Nova]] RTC & NVRAM\|\| - \|\|Write		\|#FE82\|\|%11111110 10000010\|\|[[Nova]] RTC & NVRAM\|\| - \|\|Write
	\|-		\|-
	\|#FE84 - #FEA7\|\|%11111110 10xxx1xx\|\|[~~http://shinra.cpcscene.net/willy.html~~ Willy] Future use or multi-soundchip \|\|-\|\|-		\|#FE84 - #FEA7\|\|%11111110 10xxx1xx\|\|[[Willy]] Future use or multi-soundchip \|\|-\|\|-
	\|-		\|-
	\|#FEAC - #FEAD\|\|%11111110 101011xx\|\|[~~http://shinra.cpcscene.net/willy.html~~ Willy] ~~S2P Dream SAM2965~~ MIDI synthetizer \|\|Read\|\|Write		\|#FEAC - #FEAD\|\|%11111110 101011xx\|\|[[Willy]] MIDI synthetizer \|\|Read\|\|Write
	\|-		\|-
	\|#FEB0 - #FEB7\|\|%11111110 10110xxx\|\|[[Albireo]] serial port\|\|Read\|\|Write		\|#FEB0 - #FEB7\|\|%11111110 10110xxx\|\|[[Albireo]] serial port\|\|Read\|\|Write
	\|-		\|-
	\|#FEBC - #FEBF\|\|%11111110 101111xx\|\|[~~http://shinra.cpcscene.net/willy.html~~ Willy] OPL3 \|\|-\|\|Write		\|#FEBC - #FEBF\|\|%11111110 101111xx\|\|[[Willy]] OPL3 soundcard \|\|-\|\|Write
	\|-		\|-
	\|#FEE6\|\|?\|\|Port A - [[IDE8255]]\|\|Read\|\|Write		\|#FEE6\|\|?\|\|Port A - [[IDE8255]]\|\|Read\|\|Write
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	\|#FEF0 - #FEF7\|\|%11111110 11110xxx\|\|[[uIDE 16]] - IDE registers\|\|Read\|\|Write		\|#FEF0 - #FEF7\|\|%11111110 11110xxx\|\|[[uIDE 16]] - IDE registers\|\|Read\|\|Write
	\|-		\|-
	\|#FF00 - #FFFF\|\|%11111111 xxxxxxxx\|\|AMSDAP (Amstrad MSx aDAPter, MSX-to-CPC I/O hardware interface (MSX ports #00-#ff)\|\|Read\|\|Write		\|#FF00 - #FFFF\|\|%11111111 xxxxxxxx\|\|[[AMSDAP]] (Amstrad MSx aDAPter, MSX-to-CPC I/O hardware interface (MSX ports #00-#ff)\|\|Read\|\|Write
	\|-		\|-
	\|#FF20 - #FF27\|\|%11111111 00100xxx\|\|MP3MSX (MP3 player) via AMSDAP\|\|Read\|\|Write		\|#FF20 - #FF27\|\|%11111111 00100xxx\|\|MP3MSX (MP3 player) via AMSDAP\|\|Read\|\|Write

TFM: /* I/O Port Summary */

2024-08-11T19:30:58Z

I/O Port Summary

← Older revision		Revision as of 19:30, 11 August 2024
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	\|#FBEE\|\|?\|\|[[Amstrad SSA-1 Speech Synthesizer]]\|\|Read\|\|Write		\|#FBEE\|\|?\|\|[[Amstrad SSA-1 Speech Synthesizer]]\|\|Read\|\|Write
	\|-		\|-
	\|#FBEE\|\|?\|\|[[LambdaSpeak Speech Synthesizer]]\|\|Read\|\|Write		\|#FBEE\|\|?\|\|[[LambdaSpeak III ROM\|LambdaSpeak Speech Synthesizer]]\|\|Read\|\|Write
	\|-		\|-
	\|#FBEE\|\|%xxxxx0x1 xxx0xxx0\|\|[[Kempston Mouse]] - 8bit X position\|\|Read\|\|-		\|#FBEE\|\|%xxxxx0x1 xxx0xxx0\|\|[[Kempston Mouse]] - 8bit X position\|\|Read\|\|-

Phi2x: /* Memory Mapped I/O Ports */

2024-07-05T23:19:06Z

Memory Mapped I/O Ports

← Older revision		Revision as of 23:19, 5 July 2024
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	== Memory Mapped I/O Ports ==		== Memory Mapped I/O Ports ==

	{\|~~{{Prettytable\|width: 700px; font-size: 2em;}}~~		{\| class="wikitable"
	~~\|'''~~Mem~~'''\|\|'''~~Decoded as~~'''\|\|'''~~Port~~'''\|\|'''~~Read~~'''\|\|'''~~Write~~'''~~		!Mem
			!Decoded as
			!Port
			!Read
			!Write
	\|-		\|-
	\|#4000-7FFF\|\|%01xxxxxx xxxxxxxx\|\|[[ASIC]] - CPC+/GX4000 registers\|\| Read \|\| Write		\|#4000-7FFF\|\|%01xxxxxx xxxxxxxx\|\|[[ASIC]] - CPC+/GX4000 registers\|\| Read \|\| Write

Phi2x: /* I/O Port Summary */

2024-07-05T23:18:15Z

I/O Port Summary

← Older revision		Revision as of 23:18, 5 July 2024
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	Note: While most of these devices can be reached via a range of addresses due to the partial address decoding, code should never use any address other than the canonical one (all 'x'/don't care positions filled by 1's). Otherwise multiple devices will be enabled simultaneously, which is unlikely to be what you want.		Note: While most of these devices can be reached via a range of addresses due to the partial address decoding, code should never use any address other than the canonical one (all 'x'/don't care positions filled by 1's). Otherwise multiple devices will be enabled simultaneously, which is unlikely to be what you want.

	{\|~~{{Prettytable\|width: 700px; font-size: 2em;}}~~		{\| class="wikitable"
	~~\|'''~~I/O~~'''\|\|'''~~Decoded as~~'''\|\|'''~~Port~~'''\|\|'''~~Read~~'''\|\|'''~~Write~~'''~~		!I/O
			!Decoded as
			!Port
			!Read
			!Write
	\|-		\|-
	\|#1C00\|\|%x0xxxx00 xxxxxxxx\|\|[[Dk'tronics Lightpen]] faulty mirror of #BCXX [[CRTC]] Index\|\| - \|\|Write		\|#1C00\|\|%x0xxxx00 xxxxxxxx\|\|[[Dk'tronics Lightpen]] faulty mirror of #BCXX [[CRTC]] Index\|\| - \|\|Write

TFM: /* I/O Port Summary */

2024-05-08T13:41:10Z

I/O Port Summary

← Older revision		Revision as of 13:41, 8 May 2024
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	\|-		\|-
	\|#FBEE\|\|?\|\|[[Amstrad SSA-1 Speech Synthesizer]]\|\|Read\|\|Write		\|#FBEE\|\|?\|\|[[Amstrad SSA-1 Speech Synthesizer]]\|\|Read\|\|Write
			\|-
			\|#FBEE\|\|?\|\|[[LambdaSpeak Speech Synthesizer]]\|\|Read\|\|Write
	\|-		\|-
	\|#FBEE\|\|%xxxxx0x1 xxx0xxx0\|\|[[Kempston Mouse]] - 8bit X position\|\|Read\|\|-		\|#FBEE\|\|%xxxxx0x1 xxx0xxx0\|\|[[Kempston Mouse]] - 8bit X position\|\|Read\|\|-

Phi2x: /* More Ports */

2024-04-15T20:55:48Z

More Ports

← Older revision		Revision as of 20:55, 15 April 2024
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	== More Ports ==		== More Ports ==

	Some more I/O addresses (which aren't included in the above list ~~yet~~) are here:		Some more I/O addresses (which aren't included in the above list) are here:
	* [[Schneiderware Summary]]		* [[Schneiderware Summary]]
	* [[CPCISA]]		* [[CPCISA]]

Phi2x: /* More Ports */

2024-04-15T20:55:38Z

More Ports

← Older revision		Revision as of 20:55, 15 April 2024
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	Some more I/O addresses (which aren't included in the above list yet) are here:		Some more I/O addresses (which aren't included in the above list yet) are here:
	* [[Schneiderware Summary]]		* [[Schneiderware Summary]]
			* [[CPCISA]]

	== Other I/O Ports ==		== Other I/O Ports ==

Phi2x at 15:50, 15 April 2024

2024-04-15T15:50:45Z

← Older revision		Revision as of 15:50, 15 April 2024
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	Aside from I/O addresses, there are some other important I/O signals, for example: [[NMI]] or [[External Interrupt\|INT]].		Aside from I/O addresses, there are some other important I/O signals, for example: [[NMI]] or [[External Interrupt\|INT]].

	~~== CPCISA ports for ISA cards ==~~

	~~{\|{{Prettytable\|width: 700px; font-size: 2em;}}~~
	~~\|''Device''\|\|''PC I/O range''\|\|''CPCISA high''\|\|''CPCISA low''~~
	\|-
	~~\|IDE1\|\|1F0h..1F7h\|\|#FDF0..#FDF7\|\|#FFF0..#FFF7~~
	\|-
	~~\|IDE2\|\|170h..177h\|\|#FD70..#FD77\|\|#FF70..#FF77~~
	\|-
	~~\|Joystick\|\|201h..201h\|\|#FC01..#FC01\|\|#FE01..#FE01~~
	\|-
	~~\|Ethernet\|\|210h..21Fh\|\|#FC10..#FC1F\|\|#FE10..#FE1F~~
	\|-
	~~\|Sound Blaster\|\|220h..23Fh\|\|#FC20..#FC3F\|\|#FE20..#FE3F~~
	\|-
	~~\|LPT2\|\|278h..27Fh\|\|#FC78..#FC7F\|\|#FE78..#FE7F~~
	\|-
	~~\|COM1\|\|2F8h..2FFh\|\|#FCF8..#FCFF\|\|#FEF8..#FEFF~~
	\|-
	~~\|MIDI'\|\|300h..301h\|\|#FD00..#FD01\|\|#FF00..#FF01~~
	\|-
	~~\|MIDI\|\|330h..331h\|\|#FD30..#FD31\|\|#FF30..#FF31~~
	\|-
	~~\|Sound control\|\|370h..371h\|\|#FD70..#FD71\|\|#FF70..#FF71~~
	\|-
	~~\|FDC1\|\|372h..377h\|\|#FD72..#FD77\|\|#FF72..#FF77~~
	\|-
	~~\|LPT1\|\|378h..37Fh\|\|#FD78..#FD7F\|\|#FF78..#FF7F~~
	\|-
	~~\|Sound AD-LIB\|\|388h..38Bh\|\|#FD88..#FD8B\|\|#FF88..#FF8B~~
	\|-
	~~\|VGA\|\|3B0h..3BBh\|\|#FDB0..#FDBB\|\|#FFB0..#FFBB~~
	\|-
	~~\|LPT3\|\|3BCh..3BFh\|\|#FDBC..#FDBF\|\|#FFBC..#FFBF~~
	\|-
	~~\|VGA\|\|3C0h..3DFh\|\|#FDC0..#FDCF\|\|#FFC0..#FFCF~~
	\|-
	~~\|FDC1\|\|3F2h..3F7h\|\|#FDF2..#FDF7\|\|#FFF2..#FFF7~~
	\|-
	~~\|COM1\|\|3F8h..3FFh\|\|#FDF8..#FDFF\|\|#FFF8..#FFFF~~
	\|-
	\|}

	~~== CPCISA ports for ISA motherboard ==~~

	~~{\|{{Prettytable\|width: 700px; font-size: 2em;}}~~
	~~\|''Device''\|\|''PC I/O range''\|\|''CPCISA high''\|\|''CPCISA low''~~
	\|-
	~~\|DMA\|\|000h..00Fh\|\|#FC00..#FC0F\|\|#FE00..#FE0F~~
	\|-
	~~\|interrupt\|\|020h..03Fh\|\|#FC20..#FC3F\|\|#FE20..#FE3F~~
	\|-
	~~\|counter\|\|040h..05Fh\|\|#FC40..#FC5F\|\|#FE40..#FE5F~~
	\|-
	~~\|keyboard\|\|060h..067h\|\|#FC60..#FC67\|\|#FE60..#FE67~~
	\|-
	~~\|RTC\|\|070h..071h\|\|#FC70..#FC71\|\|#FE70..#FE71~~
	\|-
	~~\|DMA\|\|080h..08Fh\|\|#FC80..#FC8F\|\|#FE80..#FE8F~~
	\|-
	~~\|DMA\|\|0C0h..0DFh\|\|#FCC0..#FCDF\|\|#FEC0..#FEDF~~
	\|-
	~~\|interrupt\|\|0A0h..0BFh\|\|#FCA0..#FCBF\|\|#FEA0..#FEBF~~
	\|-
	\|}

	[[Category:Programming]] [[Category:Stub]][[Category:CPC Internal Components]][[Category:Hardware]][[Category:Electronic Component]]		[[Category:Programming]] [[Category:Stub]][[Category:CPC Internal Components]][[Category:Hardware]][[Category:Electronic Component]]

OffseT at 08:23, 10 September 2022

2022-09-10T08:23:33Z

← Older revision		Revision as of 08:23, 10 September 2022
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	\|#F8FE\|\|%11111000 11111110\|\|[[Z-MEM]] Software Memory Configuration\|\| - \|\| Write		\|#F8FE\|\|%11111000 11111110\|\|[[Z-MEM]] Software Memory Configuration\|\| - \|\| Write
	\|-		\|-
	\|#F8FF\|\|%1111100x 111xxxxx\|\|[[CPCISA ~~by Yarek~~\|CPCISA control port]]\|\| - \|\|Write		\|#F8FF\|\|%1111100x 111xxxxx\|\|[[CPCISA\|CPCISA control port]]\|\| - \|\|Write
	\|-		\|-
	\|#F8FF\|\|%xxxxx0xx 111111xx\|\|[[Peripheral Soft Reset]] (MC_BOOT_PROGRAM and MC_START_PROGRAM do OUT [F8FF],FF)\|\| - \|\|Write		\|#F8FF\|\|%xxxxx0xx 111111xx\|\|[[Peripheral Soft Reset]] (MC_BOOT_PROGRAM and MC_START_PROGRAM do OUT [F8FF],FF)\|\| - \|\|Write
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	\|#FBFF\|\|?\|\|[[ACU Real Time Clock (DIY)]] Z80-PIO Configure Port B \|\|Read\|\|Write		\|#FBFF\|\|?\|\|[[ACU Real Time Clock (DIY)]] Z80-PIO Configure Port B \|\|Read\|\|Write
	\|-		\|-
	\|#FC00 - #FDFF\|\|%1111110x xxxxxxxx\|\|[[CPCISA ~~by Yarek~~\|CPCISA]] 16bits mode high byte latch\|\|Read\|\|Write		\|#FC00 - #FDFF\|\|%1111110x xxxxxxxx\|\|[[CPCISA\|CPCISA]] 16bits mode high byte latch\|\|Read\|\|Write
	\|-		\|-
	\|#FC00\|\|?\|\|[[M4 Board]] ACK/KICK\|\| - \|\|Write		\|#FC00\|\|?\|\|[[M4 Board]] ACK/KICK\|\| - \|\|Write
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	\|#FE00\|\|?\|\|[[M4 Board]] Data\|\| - \|\|Write		\|#FE00\|\|?\|\|[[M4 Board]] Data\|\| - \|\|Write
	\|-		\|-
	\|#FE00 - #FFFF\|\|%1111111x xxxxxxxx\|\|[[CPCISA ~~by Yarek~~\|CPCISA]] I/O access (low byte)\|\|Read\|\|Write		\|#FE00 - #FFFF\|\|%1111111x xxxxxxxx\|\|[[CPCISA\|CPCISA]] I/O access (low byte)\|\|Read\|\|Write
	\|-		\|-
	\|#FE80 - #FE81\|\|%11111110 1000000x\|\|[[Albireo]] CH376 controller\|\|Read\|\|Write		\|#FE80 - #FE81\|\|%11111110 1000000x\|\|[[Albireo]] CH376 controller\|\|Read\|\|Write