Arnold V specs - Revision history

Arnoldemu: /* Common Features */

2015-08-15T12:30:56Z

Common Features

← Older revision		Revision as of 12:30, 15 August 2015
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	The old CPC6128 keyboard is used, except that the colour scheme has been changed and the connecting cable exits in a different location.		The old CPC6128 keyboard is used, except that the colour scheme has been changed and the connecting cable exits in a different location.

			NOTE: gerald (on the forums) has confirmed a fault in the ASIC when used with external memory expansions. If a page of an external memory expansion is activated in the range &4000-&7fff and the asic ram page is active and a write is done, the write will go to the asic ram AND to the external memory expansion. This bug is NOT seen when the extra 64KB inside the 6128Plus is active when the asic ram page is active. It is advised that you set the configuration to &7fc0 before accessing the asic ram.

	===Amstrad 464 Plus===		===Amstrad 464 Plus===

Nocash at 11:08, 7 March 2010

2010-03-07T11:08:28Z

← Older revision		Revision as of 11:08, 7 March 2010
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	''Note: this is the original, unaltered document as circulated within Amstrad. It is not so much intended as a reference for Plus developers, since it contains certain errors. If you want to read a version that has been corrected at least at some points (thanks to Executioner), please go to [[Arnold_V_Specs_Revised]]''		''Note: this is the original, unaltered document as circulated within Amstrad. It is not so much intended as a reference for Plus developers, since it contains certain errors. If you want to read a version that has been corrected at least at some points (thanks to Executioner), please go to [[Arnold_V_Specs_Revised]]''

			''For more unaltered (read-only) txt/htm versions, see [[Original Arnold V Specs]]. The cpcwiki page that you are currently viewing seems to be based on the original RTF version, as indicated by the characterstically distorted printer pin-out table.''

	==PRODUCT RANGE OVERVIEW==		==PRODUCT RANGE OVERVIEW==

MacDeath at 21:22, 27 January 2010

2010-01-27T21:22:29Z

← Older revision		Revision as of 21:22, 27 January 2010
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	[[Category:CPC Plus]]		[[Category:CPC Plus]]
	[[Category:Hardware]][[Category:~~Built in Hardware~~]]		[[Category:Hardware]][[Category:CPC Internal Components]]

MacDeath at 13:40, 27 January 2010

2010-01-27T13:40:16Z

← Older revision		Revision as of 13:40, 27 January 2010
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	[[Category:CPC Plus]]		[[Category:CPC Plus]]
	[[Category:Hardware]]		[[Category:Hardware]][[Category:Built in Hardware]]

Gryzor at 16:33, 29 July 2007

2007-07-29T16:33:35Z

← Older revision		Revision as of 16:33, 29 July 2007
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	<font size="-2:>''Copyright Amstrad ©1990 plc''</font></center>		<font size="-2:>''Copyright Amstrad ©1990 plc''</font></center>

			''Note: this is the original, unaltered document as circulated within Amstrad. It is not so much intended as a reference for Plus developers, since it contains certain errors. If you want to read a version that has been corrected at least at some points (thanks to Executioner), please go to [[Arnold_V_Specs_Revised]]''

Gryzor: Reverted edits by Executioner (Talk); changed back to last version by 89.50.201.2

2007-07-29T16:32:50Z

Reverted edits by Executioner (Talk); changed back to last version by 89.50.201.2

← Older revision		Revision as of 16:32, 29 July 2007
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	A new 8 bit memory mapped register (PRI) has been added within the ASIC at address 6800h, which is cleared at power up. If zero, the normal raster interrupt mechanism functions as before. Otherwise, an interrupt occurs instead at the end of the scan line specified.. The PRI can be reprogrammed as required to produce multiple interrupts per frame. The raster interrupt occurs immediately on the leading edge of the combined logic of HSYNC active AND raster matched. The raster line is calculated as Vertical Character Count * 8 or Vertical Line Count. If the HSYNC position and duration programmed in the CRTC causes the HSYNC to still be active on the first horizontal character of a new scan line, the interrupt may occur twice for the programmed scan line (once at the start of the line, then again when the HSYNC starts at the end of the same line). See section 2.7 below for general information on interrupts.		A new 8 bit memory mapped register (PRI) has been added within the ASIC at address 6800h, which is cleared at power up. If zero, the normal raster interrupt mechanism functions as before. Otherwise, an interrupt occurs instead at the end of the scan line specified.. The PRI can be reprogrammed as required to produce multiple interrupts per frame. See section 2.7 below for general information on interrupts.


	===Soft scroll facility===		===Soft scroll facility===
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	The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.		The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.

	The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the SAR is changed, the pause counter will continue to decrement. If the DMA channel is disabled, the pause will stop decrementing for the period in which it is disabled, but it will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).		The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated.

	The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.		The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.
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	The exact timing is based on 1us cycles as follows. After the leading edge from HSYN from the 6845 there is one dead cycle followed by an instruction fetch cycle for each channel which is active (i.e. enabled and not paused). The execute cycles then follow for each active channel. All instructions execute in one cycle, except that LOAD requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the 8255, or two extra cycles if the CPU access was itself a PSG register write.		The exact timing is based on 1us cycles as follows. After the leading edge from HSYN from the 6845 there is one dead cycle followed by an instruction fetch cycle for each channel which is active (i.e. enabled and not paused). The execute cycles then follow for each active channel. All instructions execute in one cycle, except that LOAD requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the 8255, or two extra cycles if the CPU access was itself a PSG register write.

	~~===Interrupt service (Vectored interrupts)===~~

	The ASIC can produce interrupts from four sources: the raster interrupt and the three sound generator "DMA" channels. The ASIC will always supply a vector which can be used by the CPU in interrupt modes 0 and 2 or ignored in interrupt mode 1.

	The top 5 bits of the vector will be supplied from bit D7-D3 of a memory mapped interrupt vector register (IVR) at address 6805h in the ASIC, and the next two bits will determine the source of the interrupt. Bit D0 of the vector supplied is always zero.

	~~<pre>~~		===Interrupt service===
	~~D2 D1 D0~~
	~~0 0 0 DMA channel 2 interrupt vector~~
	~~0 1 0 DMA channel 1 interrupt vector~~
	~~1 0 0 DMA channel 0 interrupt vector~~
	~~1 1 0 Raster interrupt vector~~
	~~</pre>~~

	The ~~value written to bit D0 of the IVR controls whether DMA channel~~ interrupts ~~are automatically cleared. The contents of register 6805h are undefined at reset except that bit D0 will be set to 1. Software should always set up~~ the ~~IVR before placing~~ the ~~CPU in vectored interrupt mode~~.		The ASIC can produce interrupts from four sources: the raster interrupt and the three sound generator "DMA" channels.

	~~The interrupts are prioritized in~~ a ~~fixed sequence. The~~ raster interrupt ~~has~~ the ~~highest priority, followed by DMA~~ channels 2 ~~down to 0~~ respectively. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR~~. To simplify vectored interrupt systems, they may also be cleared automatically by a CPU interrupt acknowledge cycle. This feature is enabled by writing a 0 to bit D0 of IVR~~.		Bit D7 is set if the last interrupt acknowledge was for a raster interrupt. Bits D6-D4 of the DCSR are set if interrupts from sound channels 0-2 respectively are active. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR.

	Bit D7 is set if the last interrupt acknowledge was for a raster interrupt. Bits D6-D4 of the DCSR are set if interrupts from sound channels 0-2 respectively are active. These bits can be ignored by software which uses vectored interrupts where the DMA interrupts are automatically cleared, or by software which does not use the DMA channel interrupt facility. If DMA channel interrupts are used and not automatically cleared, they must be acknowledged by writing a “1” to the relevant DCSR bit. If bit D0 of the IVR is set to 0 bits D4-D6 of the DCSR will be cleared before the CPU gets a chance to read them.

	Thus interrupt service software in an environment where DMA interrupts are used must inspect these bits, giving highest priority to the raster interrupt, because this interrupt is always cleared automatically.		Thus interrupt service software in an environment where DMA interrupts are used must inspect these bits, giving highest priority to the raster interrupt, because this interrupt is always cleared automatically.
	Failure to observe this requirement may result in raster interrupts being missed.		Failure to observe this requirement may result in raster interrupts being missed. DMA interrupts must be acknowledged by writing a "1" to the relevant DCSR bit.

	~~Software which uses~~ interrupts ~~from expansion cards~~ must ~~always use Z80 non-vectored interrupt mode~~ 1~~, because the expansion bus does not support vectored interrupts.~~

	~~To summarize, vectored software should place a valid vector (D0 = 0) into~~ the ~~IVR. The hardware will supply a different vector for each interrupt source, and all interrupts are acknowledge automatically~~.

	Non vectored software must write a "1" to bit D0 of the IVR, or leave it in it's reset state. Interrupt service software must examine bit D7 of the DCSR first, followed by bits D4-D6 (in any sequence) to identify the interrupt source. DMA interrupts must be acknowledged by writing a "1" to the relevant DCSR bit.

	===Enhanced ROM cartridge support===		===Enhanced ROM cartridge support===
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	0-7 0-7		0-7 0-7

	High Bank: Logical page (DFxxh) ~~Physical page~~		High Bank: Logical page (DFxxh) 1

	0-127 (not disc page) 1		0-127 (not disc page) 1
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	The two ROM disable bits in the existing mode and ROM enable register disable the ROM as before, wherever it is mapped, as does the ROMDIS signal from the expansion bus.		The two ROM disable bits in the existing mode and ROM enable register disable the ROM as before, wherever it is mapped, as does the ROMDIS signal from the expansion bus.
	The "write through" mechanism, whereby writes to an area which is currently mapped as ROM actually write to the underlying RAM, still functions, wherever the ROM is mapped. However the write through mechanism cannot be used to access the register page. Write through also does not operate to the RAM from the register page.		The "write through" mechanism, whereby writes to an area which is currently mapped as ROM actually write to the underlying RAM, still functions, wherever the ROM is mapped. However the write through mechanism cannot be used to access the register page. Write through also does not operate to the RAM from the register page.


	===Analogue paddle ports===		===Analogue paddle ports===
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	6802h 2 N W SSA Screen split secondary start address		6802h 2 N W SSA Screen split secondary start address
	6804h 1 Y W SSCR Soft scroll control register		6804h 1 Y W SSCR Soft scroll control register
	~~6805h 1 N W IVR Interrupt Vector (Bit 0 set to 1 on reset)~~

	~~6806h~~ (unused)		6805h (unused)







			ADDR SIZE POR TYPE MNEM USE

	6808h 1 R ADC0 Analogue input channel 0		6808h 1 R ADC0 Analogue input channel 0
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	6C07h 1 (unused)		6C07h 1 (unused)
	6C08h 2 N W SAR2 "DMA" channel 2 address pointer		6C08h 2 N W SAR2 "DMA" channel 2 address pointer
	6C0Ah 1 N W PPR2 "DMA" channel 2 pause prescaler		6C0Ah 1 N W PPR2 "DMA" channel 2 pause prescaler
	6C0Bh 4 (unused)		6C0Bh 4 (unused)
	6C0Fh 1 Y R/W DCSR "DMA" control/status register</pre>		6C0Fh 1 Y R/W DCSR "DMA" control/status register</pre>

Executioner: /* Automatic feeding of sound generator */ - Pause doesn't decrement while DMA disabled

2007-07-27T06:47:30Z

Automatic feeding of sound generator: - Pause doesn't decrement while DMA disabled

← Older revision		Revision as of 06:47, 27 July 2007
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	The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.		The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.

	The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when ~~the DMA channel is disabled or~~ the SAR is changed, the pause counter will continue to decrement. It will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).		The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the SAR is changed, the pause counter will continue to decrement. If the DMA channel is disabled, the pause will stop decrementing for the period in which it is disabled, but it will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).

	The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.		The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.

Executioner: /* Interrupt service (Vectored interrupts) */ - Bit 0 tested, never set in IM0

2007-07-27T06:44:42Z

Interrupt service (Vectored interrupts): - Bit 0 tested, never set in IM0

← Older revision		Revision as of 06:44, 27 July 2007
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	The ASIC can produce interrupts from four sources: the raster interrupt and the three sound generator "DMA" channels. The ASIC will always supply a vector which can be used by the CPU in interrupt modes 0 and 2 or ignored in interrupt mode 1.		The ASIC can produce interrupts from four sources: the raster interrupt and the three sound generator "DMA" channels. The ASIC will always supply a vector which can be used by the CPU in interrupt modes 0 and 2 or ignored in interrupt mode 1.

	The top 5 bits of the vector will be supplied from bit D7-D3 of a memory mapped interrupt vector register (IVR) at address 6805h in the ASIC, and the next two bits will determine the source of the interrupt. Bit D0 of the vector supplied is ~~ignored by the Z80 in interrupt mode 2, but may be used in interrupt mode 0 (???)~~.		The top 5 bits of the vector will be supplied from bit D7-D3 of a memory mapped interrupt vector register (IVR) at address 6805h in the ASIC, and the next two bits will determine the source of the interrupt. Bit D0 of the vector supplied is always zero.

	<pre>		<pre>
	D2 D1		D2 D1 D0
	0 0 DMA channel 2 interrupt vector		0 0 0 DMA channel 2 interrupt vector
	0 1 DMA channel 1 interrupt vector		0 1 0 DMA channel 1 interrupt vector
	1 0 DMA channel 0 interrupt vector		1 0 0 DMA channel 0 interrupt vector
	1 1 Raster interrupt vector		1 1 0 Raster interrupt vector
	</pre>		</pre>

	The value written to bit D0 of the IVR controls whether DMA channel interrupts are automatically cleared~~, but has no effect on the vector itself (???)~~. The contents of register 6805h are undefined at reset except that bit D0 will be set to 1. Software should always set up the IVR before placing the CPU in vectored interrupt mode.		The value written to bit D0 of the IVR controls whether DMA channel interrupts are automatically cleared. The contents of register 6805h are undefined at reset except that bit D0 will be set to 1. Software should always set up the IVR before placing the CPU in vectored interrupt mode.

	The interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR. To simplify vectored interrupt systems, they may also be cleared automatically by a CPU interrupt acknowledge cycle. This feature is enabled by writing a 0 to bit D0 of IVR.		The interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR. To simplify vectored interrupt systems, they may also be cleared automatically by a CPU interrupt acknowledge cycle. This feature is enabled by writing a 0 to bit D0 of IVR.

Executioner: /* Programmable raster interrupt */ - Added detailed information on HSYNC/PRI interaction.

2007-07-27T02:55:22Z

Programmable raster interrupt: - Added detailed information on HSYNC/PRI interaction.

← Older revision		Revision as of 02:55, 27 July 2007
Line 153:		Line 153:


	A new 8 bit memory mapped register (PRI) has been added within the ASIC at address 6800h, which is cleared at power up. If zero, the normal raster interrupt mechanism functions as before. Otherwise, an interrupt occurs instead at the end of the scan line specified.. The PRI can be reprogrammed as required to produce multiple interrupts per frame. See section 2.7 below for general information on interrupts.		A new 8 bit memory mapped register (PRI) has been added within the ASIC at address 6800h, which is cleared at power up. If zero, the normal raster interrupt mechanism functions as before. Otherwise, an interrupt occurs instead at the end of the scan line specified.. The PRI can be reprogrammed as required to produce multiple interrupts per frame. The raster interrupt occurs immediately on the leading edge of the combined logic of HSYNC active AND raster matched. The raster line is calculated as Vertical Character Count * 8 or Vertical Line Count. If the HSYNC position and duration programmed in the CRTC causes the HSYNC to still be active on the first horizontal character of a new scan line, the interrupt may occur twice for the programmed scan line (once at the start of the line, then again when the HSYNC starts at the end of the same line). See section 2.7 below for general information on interrupts.


	===Soft scroll facility===		===Soft scroll facility===

Executioner: /* Automatic feeding of sound generator */

2007-07-27T02:45:50Z

Automatic feeding of sound generator

← Older revision		Revision as of 02:45, 27 July 2007
Line 222:		Line 222:
	The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.		The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.

	The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the DMA channel is disabled or the SAR is changed, the pause counter will continue to decrement. It will not reset and when the DMA is again enabled the command at the current SAR address will not be executed until the pause is ~~completed~~. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).		The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the DMA channel is disabled or the SAR is changed, the pause counter will continue to decrement. It will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).

	The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.		The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.