Arnold V Specs Revised - Revision history

Phi2x: /* 6845's MA */

2024-05-13T22:59:19Z

6845's MA

← Older revision		Revision as of 22:59, 13 May 2024
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	=== 6845's MA ===		=== 6845's MA ===

	NOTE: ~~It seems the~~ 6845 has an internal "stored" MA. The current MA count is reloaded with this value at the start of each line. There are 3 times when this value is updated:		NOTE: The 6845 has an internal "stored" MA. The current MA count is reloaded with this value at the start of each line. There are 3 times when this value is updated:
	# When the split screen address is set, split screen line has been reached and Horizontal Counter equals Horizontal Displayed.		# When the split screen address is set, split screen line has been reached and Horizontal Counter equals Horizontal Displayed.
	# When Raster Counter + Soft scroll matches R9 and Horizontal Counter equals Horizontal Displayed.		# When Raster Counter + Soft scroll matches R9 and Horizontal Counter equals Horizontal Displayed.

Dthrone at 17:53, 18 August 2022

2022-08-18T17:53:13Z

← Older revision		Revision as of 17:53, 18 August 2022
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	The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.		The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.

	The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the SAR is changed, the pause counter will continue to decrement. If the DMA channel is disabled, the pause will stop decrementing for the period in which it is disabled, but it will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. The ~~same~~ is ~~also true of~~ the ~~loop counter~~. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).		The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the SAR is changed, the pause counter will continue to decrement. If the DMA channel is disabled, the pause will stop decrementing for the period in which it is disabled, but it will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. The loop counter is presumably not reset either when the channel is disabled (unconfirmed). Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).

	The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.		The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.

Dthrone at 13:59, 22 July 2022

2022-07-22T13:59:11Z

← Older revision		Revision as of 13:59, 22 July 2022
Line 273:		Line 273:
	The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.		The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.

	The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the SAR is changed, the pause counter will continue to decrement. If the DMA channel is disabled, the pause will stop decrementing for the period in which it is disabled, but it will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).		The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the SAR is changed, the pause counter will continue to decrement. If the DMA channel is disabled, the pause will stop decrementing for the period in which it is disabled, but it will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. The same is also true of the loop counter. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).

	The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.		The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.

Arnoldemu: /* 8255 */

2020-07-18T17:19:22Z

8255

← Older revision		Revision as of 17:19, 18 July 2020
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	Because of timescale pressures, the data separator design in the ASIC has been deleted rather than improved . Thus all models with a disk drive use an external SED9420 data separator.		Because of timescale pressures, the data separator design in the ASIC has been deleted rather than improved . Thus all models with a disk drive use an external SED9420 data separator.

			=== 6845's MA ===

			NOTE: It seems the 6845 has an internal "stored" MA. The current MA count is reloaded with this value at the start of each line. There are 3 times when this value is updated:
			# When the split screen address is set, split screen line has been reached and Horizontal Counter equals Horizontal Displayed.
			# When Raster Counter + Soft scroll matches R9 and Horizontal Counter equals Horizontal Displayed.
			# When Vertical character count is reset to 0, it is then loaded from R12 and R13.

			It is therefore possible to simulate split screen, by setting the soft scroll at the time correct time, then setting it back to 0 immediately after.

	===8255===		===8255===

Arnoldemu: /* 6845's MA */

2020-07-18T17:19:02Z

6845's MA

← Older revision		Revision as of 17:19, 18 July 2020
Line 220:		Line 220:

	Setting the SSCR to zero, as at reset, (i.e. no offsets, no border), will of course effectively disable soft scroll.		Setting the SSCR to zero, as at reset, (i.e. no offsets, no border), will of course effectively disable soft scroll.

	~~==== 6845's MA ====~~

	~~NOTE: It seems the 6845 has an internal "stored" MA. The current MA count is reloaded with this value at the start of each line. There are 3 times when this value is updated:~~
	~~# When the split screen address is set, split screen line has been reached and Horizontal Counter equals Horizontal Displayed.~~
	~~# When Raster Counter + Soft scroll matches R9 and Horizontal Counter equals Horizontal Displayed.~~
	~~# When Vertical character count is reset to 0, it is then loaded from R12 and R13.~~

	~~It is therefore possible to simulate split screen, by setting the soft scroll at the time correct time, then setting it back to 0 immediately after.~~

	===Automatic feeding of sound generator===		===Automatic feeding of sound generator===

Arnoldemu: /* Reading of write-only I/O registers */

2020-07-18T17:18:36Z

Reading of write-only I/O registers

← Older revision		Revision as of 17:18, 18 July 2020
Line 447:		Line 447:

	Because of timescale pressures, the data separator design in the ASIC has been deleted rather than improved . Thus all models with a disk drive use an external SED9420 data separator.		Because of timescale pressures, the data separator design in the ASIC has been deleted rather than improved . Thus all models with a disk drive use an external SED9420 data separator.

			===8255===

			* When switching port A of ASICs emulated 8255 to input, FF is present on the emulated 8255's port A outputs.

			This will cause an invalid PSG register to be selected:

			ld bc,&f400
			out (c),c
			ld bc,&f6c0
			out (c),c
			ld bc,&f792
			out (c),c
			;; At this point FF appears in emulated 8255 port A. This selects an invalid PSG register '&ff', when read &FF is returned. This is one source of keyboard reading bugs.

			Therefore use this:

			ld bc,&f400
			out (c),c
			ld bc,&f6c0
			out (c),c
			ld bc,&f600 ;;; << use inactive
			out (c),c
			ld bc,&f792
			out (c),c

			* When switching input/output of port A, on a normal 8255, the outputs are all cleared to 0. This doesn't happen on the emulated 8255. This is another source of keyboard reading bugs.

	===Reading of write-only I/O registers===		===Reading of write-only I/O registers===

Arnoldemu: /* 8255 */

2020-07-18T17:18:14Z

8255

← Older revision		Revision as of 17:18, 18 July 2020
Line 229:		Line 229:

	It is therefore possible to simulate split screen, by setting the soft scroll at the time correct time, then setting it back to 0 immediately after.		It is therefore possible to simulate split screen, by setting the soft scroll at the time correct time, then setting it back to 0 immediately after.

	~~====8255====~~

	* When switching port A of ASICs emulated 8255 to input, FF is present on the emulated 8255's port A outputs.

	~~This will cause an invalid PSG register to be selected:~~

	~~ld bc,&f400~~
	~~out (c),c~~
	~~ld bc,&f6c0~~
	~~out (c),c~~
	~~ld bc,&f792~~
	~~out (c),c~~
	~~;; At this point FF appears in emulated 8255 port A. This selects an invalid PSG register '&ff', when read &FF is returned. This is one source of keyboard reading bugs.~~

	~~Therefore use this:~~

	~~ld bc,&f400~~
	~~out (c),c~~
	~~ld bc,&f6c0~~
	~~out (c),c~~
	~~ld bc,&f600 ;;; << use inactive~~
	~~out (c),c~~
	~~ld bc,&f792~~
	~~out (c),c~~

	* When switching input/output of port A, on a normal 8255, the outputs are all cleared to 0. This doesn't happen on the emulated 8255. This is another source of keyboard reading bugs.

	===Automatic feeding of sound generator===		===Automatic feeding of sound generator===

Arnoldemu: /* Automatic feeding of sound generator */

2020-07-18T17:17:55Z

Automatic feeding of sound generator

← Older revision		Revision as of 17:17, 18 July 2020
Line 257:		Line 257:
	* When switching input/output of port A, on a normal 8255, the outputs are all cleared to 0. This doesn't happen on the emulated 8255. This is another source of keyboard reading bugs.		* When switching input/output of port A, on a normal 8255, the outputs are all cleared to 0. This doesn't happen on the emulated 8255. This is another source of keyboard reading bugs.

	==Automatic feeding of sound generator==		===Automatic feeding of sound generator===

	An automatic process has been added to feed data to the sound generator from three instruction streams in main RAM without CPU intervention. Three separate channels each fetch one 16-bit instruction during horizontal retrace time. These instructions must be in usual Z-80 format, i.e. least significant bit first and must be aligned to word boundaries (i.e. address of first byte must be even). Once the three instructions have been captured , they are then executed sequentially. The maximum achievable update rate to the PSG is thus equal to the horizontal scan rate of 15.625 kHz per channel.		An automatic process has been added to feed data to the sound generator from three instruction streams in main RAM without CPU intervention. Three separate channels each fetch one 16-bit instruction during horizontal retrace time. These instructions must be in usual Z-80 format, i.e. least significant bit first and must be aligned to word boundaries (i.e. address of first byte must be even). Once the three instructions have been captured , they are then executed sequentially. The maximum achievable update rate to the PSG is thus equal to the horizontal scan rate of 15.625 kHz per channel.

Arnoldemu: /* 8255 */

2020-07-18T17:17:30Z

8255

← Older revision		Revision as of 17:17, 18 July 2020
Line 230:		Line 230:
	It is therefore possible to simulate split screen, by setting the soft scroll at the time correct time, then setting it back to 0 immediately after.		It is therefore possible to simulate split screen, by setting the soft scroll at the time correct time, then setting it back to 0 immediately after.

	==8255==		====8255====

	* When switching port A of ASICs emulated 8255 to input, FF is present on the emulated 8255's port A outputs.		* When switching port A of ASICs emulated 8255 to input, FF is present on the emulated 8255's port A outputs.

Arnoldemu: /* 6845's MA */

2020-07-18T17:17:19Z

6845's MA

← Older revision		Revision as of 17:17, 18 July 2020
Line 221:		Line 221:
	Setting the SSCR to zero, as at reset, (i.e. no offsets, no border), will of course effectively disable soft scroll.		Setting the SSCR to zero, as at reset, (i.e. no offsets, no border), will of course effectively disable soft scroll.

	== 6845's MA ==		==== 6845's MA ====

	NOTE: It seems the 6845 has an internal "stored" MA. The current MA count is reloaded with this value at the start of each line. There are 3 times when this value is updated:		NOTE: It seems the 6845 has an internal "stored" MA. The current MA count is reloaded with this value at the start of each line. There are 3 times when this value is updated: