Aleste Translation PROMs and EPROMs - Revision history

MacDeath at 00:28, 17 December 2010

2010-12-17T00:28:11Z

← Older revision		Revision as of 00:28, 17 December 2010
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	07E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF		07E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
	07F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF		07F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

			[[Category:Non CPC Computers]][[Category:Clones]]

Nocash: /* Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) */

2010-02-23T20:40:06Z

Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank)

← Older revision		Revision as of 20:40, 23 February 2010
Line 61:		Line 61:
	0208..02FF: filled with 01 ;/07h to 2 (amsdos), others to 1 (basic)		0208..02FF: filled with 01 ;/07h to 2 (amsdos), others to 1 (basic)
	Address FABFh: Ext Port		Address FABFh: Ext Port
	~~0700~~..~~07FF~~: filled with incrementing values: 00h..FFh		0300..03FF: filled with incrementing values: 00h..FFh

	== Aleste MAPPER prom (Gate Array 3, RAM banking) ==		== Aleste MAPPER prom (Gate Array 3, RAM banking) ==

Nocash: /* Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) */

2010-02-23T20:39:39Z

Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank)

← Older revision		Revision as of 20:39, 23 February 2010
Line 60:		Line 60:
	0200..0207: 01 01 01 03 01 01 01 02 ;\translates bank 03h to 3 (menu), bank		0200..0207: 01 01 01 03 01 01 01 02 ;\translates bank 03h to 3 (menu), bank
	0208..02FF: filled with 01 ;/07h to 2 (amsdos), others to 1 (basic)		0208..02FF: filled with 01 ;/07h to 2 (amsdos), others to 1 (basic)
			Address FABFh: Ext Port
			0700..07FF: filled with incrementing values: 00h..FFh

	== Aleste MAPPER prom (Gate Array 3, RAM banking) ==		== Aleste MAPPER prom (Gate Array 3, RAM banking) ==

Nocash: /* Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) */

2010-02-23T20:33:47Z

Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank)

← Older revision		Revision as of 20:33, 23 February 2010
Line 21:		Line 21:
	01C0..01FF: 7FFFh Gate Array 3 (rambank, etc.)		01C0..01FF: 7FFFh Gate Array 3 (rambank, etc.)
	0200..02FF: DFFFh Upper ROM Bank		0200..02FF: DFFFh Upper ROM Bank
	0300..03FF: ~~FFFFh~~ ~~Not used~~ (filled with incrementing values: 00h..FFh)		0300..03FF: FABFh Ext Port (filled with incrementing values: 00h..FFh)
	Part B (when MAPMOD=1)		Part B (when MAPMOD=1)
	0400..04FF: 5FFFh Not used (same as MAPMODE=0)		0400..04FF: 5FFFh Not used (same as MAPMODE=0)
Line 29:		Line 29:
	05C0..05FF: 7FFFh Gate Array 3 (rambank, etc.) (same as MAPMODE=0)		05C0..05FF: 7FFFh Gate Array 3 (rambank, etc.) (same as MAPMODE=0)
	0600..06FF: DFFFh Upper ROM Bank (same as MAPMODE=0)		0600..06FF: DFFFh Upper ROM Bank (same as MAPMODE=0)
	0700..07FF: ~~FFFFh~~ ~~Not used~~ (same as MAPMODE=0)		0700..07FF: FABFh Ext Port (same as MAPMODE=0)

	Address 7FFFh: Gate Array 0: (A13=1, A15=0, DataIn=00h..3Fh) palette index		Address 7FFFh: Gate Array 0: (A13=1, A15=0, DataIn=00h..3Fh) palette index

Nocash: /* Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) */

2010-02-08T00:46:22Z

Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank)

Nocash: /* Aleste VDKEY eprom (video and keyboard) */

2010-02-08T00:37:03Z

Aleste VDKEY eprom (video and keyboard)

← Older revision		Revision as of 00:37, 8 February 2010
Line 138:		Line 138:

	Inputs:		Inputs:
	A0..A8 9bit counter ~~(clocked by 3CY aka 1M div sth, reset by HY aka VSYNC)~~		A0..A8 9bit scanline counter
	A9 ~~clocked by~~ 1M div ~~sth~~		A9 HSYNC period (duration counted as 1M div 8 or so)
	A10 not used (wired to GND)		A10 not used (wired to GND)
	Outputs:		Outputs:
Line 169:		Line 169:
	0200..03FF: Same as 0000h..01FFh, but with D0 inverted		0200..03FF: Same as 0000h..01FFh, but with D0 inverted
	(ie. "A A F B B B A A 8 8 8 8 8 8 8 8" etc.)		(ie. "A A F B B B A A 8 8 8 8 8 8 8 8" etc.)
			(that is, SYNC is inverted during HSYNC period)

	* Note: The "." entries contain a value of 9. (The "." is just used instead of "9" to make the other entries more visible)		* Note: The "." entries contain a value of 9. (The "." is just used instead of "9" to make the other entries more visible)

Nocash at 23:11, 7 February 2010

2010-02-07T23:11:56Z

← Older revision		Revision as of 23:11, 7 February 2010
Line 1:		Line 1:
	Aside from the BIOS EPROM, the [[Aleste 520EX]] contains five Translation PROMs and EPROMs. They aren't accessible as memory to the CPU, but rather used ~~to translate an~~ incoming signals (through address inputs) to to outgoing signals (through data outputs).		Aside from the BIOS EPROM, the [[Aleste 520EX]] contains five Translation PROMs and EPROMs. They aren't accessible as memory to the CPU, but rather used as "logic look-up tables", translating incoming signals (through address inputs) to to outgoing signals (through data outputs).

	== Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) ==		== Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) ==

Nocash: /* Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) */

2010-02-07T18:37:36Z

Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank)

← Older revision		Revision as of 18:37, 7 February 2010
Line 38:		Line 38:
	Address 7FFFh: Gate Array 1: (A13=1, A15=0, DataIn=40h..7Fh) palette data		Address 7FFFh: Gate Array 1: (A13=1, A15=0, DataIn=40h..7Fh) palette data
	When MAPMOD=0		When MAPMOD=0
	0140: 15 15 1C 1F 10 13 14 17 13 1F 0F 3F 03 33 07 37 ;\		0140: 15 15 1C 1F 10 13 14 17 13 1F 0F 3F 03 33 07 37 ;\27-color palette
	0150: 10 1C 0C 3C 00 30 04 34 11 1D 0D 3D 01 31 05 35 ; ~~27-color palette~~		0150: 10 1C 0C 3C 00 30 04 34 11 1D 0D 3D 01 31 05 35 ;/
	0160: 15 15 1C 1F 10 13 14 17 13 1F 0F 3F 03 33 07 37 ;		0160: 15 15 1C 1F 10 13 14 17 13 1F 0F 3F 03 33 07 37 ;\27-color palette (same as above)
	0170: 10 1C 0C 3C 00 30 04 34 11 1D 0D 3D 01 31 05 35 ;/		0170: 10 1C 0C 3C 00 30 04 34 11 1D 0D 3D 01 31 05 35 ;/
	When MAPMOD=1		When MAPMOD=1

Nocash: /* Aleste MAPPER prom (Gate Array 3, RAM banking) */

2010-02-07T18:34:23Z

Aleste MAPPER prom (Gate Array 3, RAM banking)

← Older revision		Revision as of 18:34, 7 February 2010
Line 88:		Line 88:
	0060: 8 8 8 8 9 9 9 9 A A A A B B B B ;		0060: 8 8 8 8 9 9 9 9 A A A A B B B B ;
	0070: C C C C D D D D E E E E F F F F ;/		0070: C C C C D D D D E E E E F F F F ;/
	00C0: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 ;\		00C0: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 ;\second 256K
	00D0: 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 ; ~~second 256K~~		00D0: 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 ; (fifth bit is handled elsewhere: bit4 is ANDed
	00E0: 8 8 8 8 9 9 9 9 A A A A B B B B ; ~~(fifth bit stored elsewhere?~~)		00E0: 8 8 8 8 9 9 9 9 A A A A B B B B ; with MAPMOD and then passed to MAP18 directly)
	00F0: C C C C D D D D E E E E F F F F ;/		00F0: C C C C D D D D E E E E F F F F ;/
	Allows to map any bank to any location (similar to the RAM "mappers" in MSX		Allows to map any bank to any location (similar to the RAM "mappers" in MSX

Nocash: /* Aleste ROMRAM prom (Gate Array 2, ROM/RAM enable) */

2010-02-06T17:42:16Z

Aleste ROMRAM prom (Gate Array 2, ROM/RAM enable)

← Older revision		Revision as of 00:46, 8 February 2010
Line 15:		Line 15:
	Part A (when MAPMOD=0)		Part A (when MAPMOD=0)
	COLDAT Addr CPU Addr Content		COLDAT Addr CPU Addr Content
	0000..00FF: 5FFFh ? (filled with incrementing values: 00h..FFh)		0000..00FF: 5FFFh Not used (filled with incrementing values: 00h..FFh)
	0100..013F: 7FFFh Gate Array 0 (palette index)		0100..013F: 7FFFh Gate Array 0 (palette index)
	0140..017F: 7FFFh Gate Array 1 (palette data)		0140..017F: 7FFFh Gate Array 1 (palette data)
Line 21:		Line 21:
	01C0..01FF: 7FFFh Gate Array 3 (rambank, etc.)		01C0..01FF: 7FFFh Gate Array 3 (rambank, etc.)
	0200..02FF: DFFFh Upper ROM Bank		0200..02FF: DFFFh Upper ROM Bank
	0300..03FF: FFFFh ? (filled with incrementing values: 00h..FFh)		0300..03FF: FFFFh Not used (filled with incrementing values: 00h..FFh)
	Part B (when MAPMOD=1)		Part B (when MAPMOD=1)
	0400..04FF: 5FFFh ? (~~filled with incrementing values: 00h..FFh~~)		0400..04FF: 5FFFh Not used (same as MAPMODE=0)
	0500..053F: 7FFFh Gate Array 0 (palette index) (same as MAPMODE=0)		0500..053F: 7FFFh Gate Array 0 (palette index) (same as MAPMODE=0)
	0540..057F: 7FFFh Gate Array 1 (palette data) (other than MAPMODE=0)		0540..057F: 7FFFh Gate Array 1 (palette data) (other than MAPMODE=0)
Line 29:		Line 29:
	05C0..05FF: 7FFFh Gate Array 3 (rambank, etc.) (same as MAPMODE=0)		05C0..05FF: 7FFFh Gate Array 3 (rambank, etc.) (same as MAPMODE=0)
	0600..06FF: DFFFh Upper ROM Bank (same as MAPMODE=0)		0600..06FF: DFFFh Upper ROM Bank (same as MAPMODE=0)
	0700..07FF: FFFFh ? (~~filled with incrementing values: 00h..FFh~~)		0700..07FF: FFFFh Not used (same as MAPMODE=0)

	Address 7FFFh: Gate Array 0: (A13=1, A15=0, DataIn=00h..3Fh) palette index		Address 7FFFh: Gate Array 0: (A13=1, A15=0, DataIn=00h..3Fh) palette index
	0100: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ;pen index		0100: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ;-pen index
	0110: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ;border		0110: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ;-border (only bit4 is relevant here)
	0120: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F ;~~? NCOLOR4~~		0120: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F ;\same of above
	0130: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ;~~? NCOLOR4~~		0130: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ;/(but, with bit5 set, which has no function)
	Address 7FFFh: Gate Array 1: (A13=1, A15=0, DataIn=40h..7Fh) palette data		Address 7FFFh: Gate Array 1: (A13=1, A15=0, DataIn=40h..7Fh) palette data
	When MAPMOD=0		When MAPMOD=0
Line 48:		Line 48:
	0570: 03 13 23 33 07 17 27 37 0B 1B 2B 3B 0F 1F 2F 3F ;/		0570: 03 13 23 33 07 17 27 37 0B 1B 2B 3B 0F 1F 2F 3F ;/
	Address 7FFFh: Gate Array 2: (A13=1, A15=0, DataIn=80h..BFh) vmode, rom, leds		Address 7FFFh: Gate Array 2: (A13=1, A15=0, DataIn=80h..BFh) vmode, rom, leds
	0180: 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F		0180: 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ;\just a 1:1 translation,
	0190: 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F		0190: 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F ; increasing values 00h..3Fh
	01A0: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF		01A0: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF ; (but, with bit7=set=blah)
	01B0: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF		01B0: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF ;/
	Address 7FFFh: Gate Array 3: (A13=1, A15=0, DataIn=C0h..FFh) ram bank,		Address 7FFFh: Gate Array 3: (A13=1, A15=0, DataIn=C0h..FFh) ram bank,
	01C0: 80 81 82 83 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ;\basically incrementing		01C0: 80 81 82 83 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ;\basically incrementing
	01D0: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ; values 00h..3Fh, but		01D0: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ; values 00h..3Fh, but
	01E0: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F ; with bit7=1 in ~~first~~		01E0: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F ; with bit7=1=VRAMACC in
	01F0: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ;/four values		01F0: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ;/first four values
	Address DFFFh: Upper ROM Bank: (A13=0, A15=1)		Address DFFFh: Upper ROM Bank: (A13=0, A15=1)
	0200..0207: 01 01 01 03 01 01 01 02 ;\translates bank 03h to 3 (menu), bank		0200..0207: 01 01 01 03 01 01 01 02 ;\translates bank 03h to 3 (menu), bank

← Older revision		Revision as of 17:42, 6 February 2010
Line 109:		Line 109:
	A7 RAMDIS ;-RAMDIS pin on expansion port		A7 RAMDIS ;-RAMDIS pin on expansion port
	Outputs:		Outputs:
	D0 BUFFER0 ?		D0 BUFFER0 ;set LOW on read from even RAM address (16bit-to-8bit bus)
	D1 BUFFER1 ?		D1 BUFFER1 ;set LOW on read from odd RAM address (16bit-to-8bit bus)
	D2 /ROMEN ;ROM enable (note: ROMDIS is handled elsewhere)		D2 /ROMEN ;ROM enable (note: ROMDIS is handled elsewhere)
	D3 /RAMEN ;RAM enable		D3 /RAMEN ;RAM enable
Line 116:		Line 116:
	Page: 0000h 4000h 8000h C000h		Page: 0000h 4000h 8000h C000h
	----------------------------------------		----------------------------------------
	0000: B 6 B 6 6 6 6 6 6 6 6 6 B B 6 6		0000: B 6 B 6 6 6 6 6 6 6 6 6 B B 6 6 ;even addresses
	0010: B 5 B 5 5 5 5 5 5 5 5 5 B B 5 5		0010: B 5 B 5 5 5 5 5 5 5 5 5 B B 5 5 ;odd addresses
	0020: F F F F F F F F F F F F F F F F ;\inactive because /MREQ=high		0020: F F F F F F F F F F F F F F F F ;\inactive because /MREQ=high
	0030: F F F F F F F F F F F F F F F F ;/		0030: F F F F F F F F F F F F F F F F ;/
Line 125:		Line 125:
	0070: F F F F F F F F F F F F F F F F ;/		0070: F F F F F F F F F F F F F F F F ;/
	0080: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ;\		0080: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ;\
	0090: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ;		0090: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ; same as above, but BUFFER0 and BUFFER1 bits all SET
	00A0: F F F F F F F F F F F F F F F F ; ~~similar to above~~		00A0: F F F F F F F F F F F F F F F F ; (reading from internal RAM forcefully disabled via
	00B0: F F F F F F F F F F F F F F F F ; ~~(internal RAM forcefully disabled via~~		00B0: F F F F F F F F F F F F F F F F ; RAMDIS signal from expansion port)
	00C0: F F F F F F F F F F F F F F F F ; ~~RAMDIS signal from expansion port)~~		00C0: F F F F F F F F F F F F F F F F ; (however WRITING to RAM isn't disabled, the "7" means
	00D0: F F F F F F F F F F F F F F F F ; ~~... hmm~~, ~~he "B" and "7" values do what exactly ?~~		00D0: F F F F F F F F F F F F F F F F ; signal /RAMEN=LOW, so writing is possible)
	00E0: F F F F F F F F F F F F F F F F ;		00E0: F F F F F F F F F F F F F F F F ;
	00F0: F F F F F F F F F F F F F F F F ;/		00F0: F F F F F F F F F F F F F F F F ;/