Aleste 520EX - I/O Ports - Revision history

Xolod: /* Gate Array Register 2 - Video Mode, ROM enable, LEDs */

2019-12-13T11:03:23Z

Gate Array Register 2 - Video Mode, ROM enable, LEDs

2010-12-17T00:27:15Z

← Older revision		Revision as of 00:27, 17 December 2010
Line 352:		Line 352:
	The built-in RS232 port can be used to connect a serial mouse.		The built-in RS232 port can be used to connect a serial mouse.
	* See [[Serial RS232 Mouse]] for details on the protocol		* See [[Serial RS232 Mouse]] for details on the protocol

			[[Category:Non CPC Computers]][[Category:Clones]]

2010-03-01T11:10:18Z

Upper ROM Bank

← Older revision		Revision as of 11:10, 1 March 2010
Line 227:		Line 227:
	07h AMSDOS (bytes in 8000h..BFFFh in the Aleste's 64K EPROM)		07h AMSDOS (bytes in 8000h..BFFFh in the Aleste's 64K EPROM)
	All other values 01h..02h, 04h..06h, 08h..FFh do select BASIC, too.		All other values 01h..02h, 04h..06h, 08h..FFh do select BASIC, too.

			The BOOTMENU is an aleste specific ROM bank. BASIC and AMSDOS are 1:1 same as in CPC6128. The BIOS (lower ROM bank) is almost same as in CPC6128 (only the Startup Message and Printer handling are modified). For details, see:
			* [[Media:AlesteBiosDisassembly.txt]] - Disassembly of differences between CPC6128 and Aleste BIOS
			* [[Media:AlesteBootmenuRomBank3.asm]] - Original source code for BOOTMENU (Upper ROM Bank 3)

	== PPI 8255 ==		== PPI 8255 ==

2010-02-28T10:13:20Z

Ext Port (Port FABFh)

← Older revision		Revision as of 10:13, 28 February 2010
Line 66:		Line 66:
	* 1 = Reserved (would access both PSG and 8253 together)		* 1 = Reserved (would access both PSG and 8253 together)
	* 2 = RTC (Real-Time Clock) (With PPI.Port C: Bit2=DS, Bit1=AS, Bit0=R/W. So combinations are 2, write address, 4 write data, 5 read data)		* 2 = RTC (Real-Time Clock) (With PPI.Port C: Bit2=DS, Bit1=AS, Bit0=R/W. So combinations are 2, write address, 4 write data, 5 read data)
	* 3 = ~~8254~~ (Baudrate/Future Timer) (With address lines A0 and A1 = register selection)		* 3 = 8253 (Baudrate/Future Timer) (With address lines A0 and A1 = register selection)
	\|-		\|-
	\|3\|\|force video to black		\|3\|\|force video to black

2010-02-28T10:11:57Z

I/O Map (Overview)

← Older revision		Revision as of 10:11, 28 February 2010
Line 39:		Line 39:
	\|-		\|-
	\|#FA7E\|\|%xxxxx0x0 0xxxxxxx\|\|Floppy Motor Control (for [[765 FDC]])\|\| - \|\|Write		\|#FA7E\|\|%xxxxx0x0 0xxxxxxx\|\|Floppy Motor Control (for [[765 FDC]])\|\| - \|\|Write
			\|-
			\|#FABC\|\|%xxxxx0x0 10xxxx00\|\|Aleste EXTPORT with CS53: Forward PPI Port A to 8253 Timer 0\|\| - \|\|Write
			\|-
			\|#FABD\|\|%xxxxx0x0 10xxxx01\|\|Aleste EXTPORT with CS53: Forward PPI Port A to 8253 Timer 1\|\| - \|\|Write
			\|-
			\|#FABE\|\|%xxxxx0x0 10xxxx10\|\|Aleste EXTPORT with CS53: Forward PPI Port A to 8253 Timer 2\|\| - \|\|Write
			\|-
			\|#FABF\|\|%xxxxx0x0 10xxxx11\|\|Aleste EXTPORT with CS53: Forward PPI Port A to 8253 Control\|\| - \|\|Write
	\|-		\|-
	\|#FABF\|\|%xxxxx0x0 10xxxxxx\|\|Aleste EXTPORT\|\| - \|\|Write		\|#FABF\|\|%xxxxx0x0 10xxxxxx\|\|Aleste EXTPORT\|\| - \|\|Write

2010-02-23T21:13:38Z

Ext Port (Port FABFh)

← Older revision		Revision as of 21:13, 23 February 2010
Line 52:		Line 52:
	\|''bit''\|\|Action		\|''bit''\|\|Action
	\|-		\|-
	\|7\|\|not used		\|7-6\|\|not used
	\|-		\|-
	\|6\|\|~~not used~~		\|5-4\|\|PPI Port A usage
	\|-		* 0 = PSG (Sound Chip; default, as in CPC) (With PPI.Port C: BC1/BDIR)
	~~\|5\|\|if~~ 0, ~~then AY is accessed when read~~/~~write to 8255 port A, if~~ 1 ~~then real~~-~~time clock is accessed with read/write to 8255 port A. When real-time clock is selected, bits 2.~~.~~0 of PPI port~~ C ~~are used to define real-time clock operation.~~ DS ~~bit 2~~, AS ~~bit 1~~, R/W ~~bit 0~~. So combinations are 2, write address, 4 write data, 5 read data.		* 1 = Reserved (would access both PSG and 8253 together)
	\|-		* 2 = RTC (Real-Time Clock) (With PPI.Port C: Bit2=DS, Bit1=AS, Bit0=R/W. So combinations are 2, write address, 4 write data, 5 read data)
	~~\|4\|\|Enable 8253 timer. Any I~~/~~O write then accesses 8253 with data comming from 8255 port A. Bit~~ A0/A1 ~~of I/O port defines 8253~~ register		* 3 = 8254 (Baudrate/Future Timer) (With address lines A0 and A1 = register selection)
	\|-		\|-
	\|3\|\|force video to black		\|3\|\|force video to black

2010-02-22T14:08:51Z

I/O Map (Overview)

← Older revision		Revision as of 14:08, 22 February 2010
Line 26:		Line 26:
	\|#DFXX\|\|%xx0xxxxx xxxxxxxx\|\|[[Upper ROM Bank Number]] (bank 3 = Aleste Bootmenu)\|\| - \|\|Write		\|#DFXX\|\|%xx0xxxxx xxxxxxxx\|\|[[Upper ROM Bank Number]] (bank 3 = Aleste Bootmenu)\|\| - \|\|Write
	\|-		\|-
	\|#EEXX\|\|%xxx0xxx0 xxxxxxxx\|\|Aleste [[8251 USART chip]] (RS232/Mouse) Data\|\| ? \|\|Write		\|#EEXX\|\|%xxx0xxx0 xxxxxxxx\|\|Aleste [[8251 USART chip]] (RS232/Mouse) Data\|\| Read \|\|Write
	\|-		\|-
	\|#EFXX\|\|%xxx0xxx1 xxxxxxxx\|\|Aleste [[8251 USART chip]] (RS232/Mouse) Control\|\| ? \|\|Write		\|#EFXX\|\|%xxx0xxx1 xxxxxxxx\|\|Aleste [[8251 USART chip]] (RS232/Mouse) Control/Status\|\| Read \|\|Write
	\|-		\|-
	\|#F4XX\|\|%xxxx0x00 xxxxxxxx\|\|[[8255]] PIO Port A (PSG/8253 Timer/Real-Time Clock data)\|\|Read\|\|Write		\|#F4XX\|\|%xxxx0x00 xxxxxxxx\|\|[[8255]] PIO Port A (PSG/8253 Timer/Real-Time Clock data)\|\|Read\|\|Write

2010-02-22T12:40:51Z

PPI Port A (Port F4xxh)

← Older revision		Revision as of 12:40, 22 February 2010
Line 235:		Line 235:
	Ext Port (Port FABFh) controls whether PSG, RTC, or Timer is selected.		Ext Port (Port FABFh) controls whether PSG, RTC, or Timer is selected.
	* For info on Baudrate/Future Timer see [[8253 chip]].		* For info on Baudrate/Future Timer see [[8253 chip]].
			* For info on Real Time Clock see [[PC compatible RTC chip]].

	=== PPI Port B (Port F5xxh) ===		=== PPI Port B (Port F5xxh) ===

2010-02-22T04:07:37Z

I/O Map (Overview)

← Older revision		Revision as of 04:07, 22 February 2010
Line 26:		Line 26:
	\|#DFXX\|\|%xx0xxxxx xxxxxxxx\|\|[[Upper ROM Bank Number]] (bank 3 = Aleste Bootmenu)\|\| - \|\|Write		\|#DFXX\|\|%xx0xxxxx xxxxxxxx\|\|[[Upper ROM Bank Number]] (bank 3 = Aleste Bootmenu)\|\| - \|\|Write
	\|-		\|-
	\|#EEXX\|\|%xxx0xxx0 xxxxxxxx\|\|Aleste USART ~~8251~~ (RS232/Mouse) Data\|\| ? \|\|Write		\|#EEXX\|\|%xxx0xxx0 xxxxxxxx\|\|Aleste [[8251 USART chip]] (RS232/Mouse) Data\|\| ? \|\|Write
	\|-		\|-
	\|#EFXX\|\|%xxx0xxx1 xxxxxxxx\|\|Aleste USART ~~8251~~ (RS232/Mouse) Control\|\| ? \|\|Write		\|#EFXX\|\|%xxx0xxx1 xxxxxxxx\|\|Aleste [[8251 USART chip]] (RS232/Mouse) Control\|\| ? \|\|Write
	\|-		\|-
	\|#F4XX\|\|%xxxx0x00 xxxxxxxx\|\|[[8255]] PIO Port A (PSG/8253 Timer/Real-Time Clock data)\|\|Read\|\|Write		\|#F4XX\|\|%xxxx0x00 xxxxxxxx\|\|[[8255]] PIO Port A (PSG/8253 Timer/Real-Time Clock data)\|\|Read\|\|Write

2010-02-22T03:21:37Z

PPI Port A (Port F4xxh)

← Older revision		Revision as of 03:21, 22 February 2010
Line 232:		Line 232:
	\|-		\|-
	\|}		\|}

			Ext Port (Port FABFh) controls whether PSG, RTC, or Timer is selected.
			* For info on Baudrate/Future Timer see [[8253 chip]].

	=== PPI Port B (Port F5xxh) ===		=== PPI Port B (Port F5xxh) ===