Action Replay AMX - Revision history

Phi2x: /* Technical */

2025-02-23T22:01:47Z

Technical

← Older revision		Revision as of 22:01, 23 February 2025
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	== Technical ==		== Technical ==

	* The eagle schematics indicate INT is triggered, but the PCB drawings indicate NMI is connected.		* The eagle schematics indicate INT is triggered, but the PCB drawings indicate [[NMI]] is connected.
	* the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.		* the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.
	* Has a write only I/O port where A10=0 and A2=0. A8 of the port address (when '1'?) is used to 'activate' the ROMDIS signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.		* Has a write only I/O port where A10=0 and A2=0. A8 of the port address (when '1'?) is used to 'activate' the ROMDIS signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.

Phi2x: /* Pictures */

2024-06-03T11:38:29Z

Pictures

← Older revision		Revision as of 11:38, 3 June 2024
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	image:Datel_ActionReplayAMX_PCB_Top.jpg\|PCB Top		image:Datel_ActionReplayAMX_PCB_Top.jpg\|PCB Top
	image:Datel_ActionReplayAMX_PCB_Bottom.jpg\|PCB Bottom		image:Datel_ActionReplayAMX_PCB_Bottom.jpg\|PCB Bottom
			image:Amstrad-CPC-Action-Replay-AMX-case.png\|Unit front
			image:Amstrad-CPC-Action-Replay-AMX-PCB.png\|PCB Top

	</gallery>		</gallery>

Arnoldemu: /* Technical */

2021-05-07T08:50:06Z

Technical

← Older revision		Revision as of 08:50, 7 May 2021
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	== Technical ==		== Technical ==

	* The eagle schematics indicate INT is triggered, but the ~~layouts~~ indicate NMI is connected.		* The eagle schematics indicate INT is triggered, but the PCB drawings indicate NMI is connected.
	* the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.		* the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.
	* Has a write only I/O port where A10=0 and A2=0. A8 of the port address (when '1'?) is used to 'activate' the ROMDIS signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.		* Has a write only I/O port where A10=0 and A2=0. A8 of the port address (when '1'?) is used to 'activate' the ROMDIS signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.

Arnoldemu: /* Technical */

2021-05-07T08:48:33Z

Technical

← Older revision		Revision as of 08:48, 7 May 2021
Line 13:		Line 13:
	== Technical ==		== Technical ==

			* The eagle schematics indicate INT is triggered, but the layouts indicate NMI is connected.
	* the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.		* the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.
	* Has a write only I/O port where A10=0 and A2=0. A8 of the port address (when '1'?) is used to 'activate' the ROMDIS signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.		* Has a write only I/O port where A10=0 and A2=0. A8 of the port address (when '1'?) is used to 'activate' the ROMDIS signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.

Arnoldemu: /* Technical */

2021-05-01T15:41:45Z

Technical

← Older revision		Revision as of 15:41, 1 May 2021
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	== Technical ==		== Technical ==

	* Has a write only I/O port ~~&FBFB/&FAFB (partially decoded.~~ A10=0, A2=0). A8 ~~controls~~ ROMDIS~~/RAMDIS~~ signal. ~~Cleared by RESET~~.		* the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.
	* Freeze button seems to trigger normal interrupt (~~not NMI~~?)		* Has a write only I/O port where A10=0 and A2=0. A8 of the port address (when '1'?) is used to 'activate' the ROMDIS signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.
	* Seems like there is ~~rom and ram~~ access.		It's not clear how the entire space can be written to.

	* The unit has a switch for load/save, looks like A12 is driven depending on that.		* The unit has a switch for load/save, looks like A12 is driven depending on that.

			All the above has been derived from schematics so may be wrong. This needs testing.

	== Pictures ==		== Pictures ==

Arnoldemu: /* Technical */

2020-10-18T16:37:35Z

Technical

← Older revision		Revision as of 16:37, 18 October 2020
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	* Has a write only I/O port &FBFB/&FAFB (partially decoded. A10=0, A2=0). A8 controls ROMDIS/RAMDIS signal. Cleared by RESET.		* Has a write only I/O port &FBFB/&FAFB (partially decoded. A10=0, A2=0). A8 controls ROMDIS/RAMDIS signal. Cleared by RESET.
	* Freeze button seems to trigger normal interrupt (not NMI?)		* Freeze button seems to trigger normal interrupt (not NMI?)
			* Seems like there is rom and ram access.
			* The unit has a switch for load/save, looks like A12 is driven depending on that.

	== Pictures ==		== Pictures ==

Arnoldemu: /* Technical */

2020-10-18T16:26:22Z

Technical

← Older revision		Revision as of 16:26, 18 October 2020
Line 13:		Line 13:
	== Technical ==		== Technical ==

	* Has a write only I/O port &FBFB/&FAFB (partially decoded. A10=0, A2=0). A8 controls ROMDIS/RAMDIS signal.		* Has a write only I/O port &FBFB/&FAFB (partially decoded. A10=0, A2=0). A8 controls ROMDIS/RAMDIS signal. Cleared by RESET.
			* Freeze button seems to trigger normal interrupt (not NMI?)

	== Pictures ==		== Pictures ==

Arnoldemu: /* Technical */

2020-10-18T16:23:23Z

Technical

← Older revision		Revision as of 16:23, 18 October 2020
Line 13:		Line 13:
	== Technical ==		== Technical ==

	* Has a write only I/O port &FBFB (partially decoded. A10=0, A2=0)		* Has a write only I/O port &FBFB/&FAFB (partially decoded. A10=0, A2=0). A8 controls ROMDIS/RAMDIS signal.

	== Pictures ==		== Pictures ==

Arnoldemu: /* Pictures */

2020-10-18T16:15:37Z

Pictures

← Older revision		Revision as of 16:15, 18 October 2020
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	The hardware only has RAM and not ROM, therefore the device needs software programmed into the RAM to use it.		The hardware only has RAM and not ROM, therefore the device needs software programmed into the RAM to use it.

			== Technical ==

			* Has a write only I/O port &FBFB (partially decoded. A10=0, A2=0)

	== Pictures ==		== Pictures ==

Cpcmaniaco: /* Weblinks */

2020-09-18T10:23:49Z

Weblinks

← Older revision		Revision as of 10:23, 18 September 2020
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	* [https://cpcrulez.fr/hardware-interface_debug-action_replay_AMX_AC.htm ''Action Replay AMX'' from CPCrulez]		* [https://cpcrulez.fr/hardware-interface_debug-action_replay_AMX_AC.htm ''Action Replay AMX'' from CPCrulez]
			* [http://hardware.speccy.org/temp/Amstrad-ARM.html ''Action Replay AMX'' from hardware.speccy.org]

	[[Category:Peripherals]] [[Category:Copy Protection]]		[[Category:Peripherals]] [[Category:Copy Protection]]