8255 - Revision history

Phi2x: /* PPI Port B */

2025-03-30T12:40:50Z

PPI Port B

← Older revision		Revision as of 12:40, 30 March 2025
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	\|-		\|-
	\|3\|\|LK3\|\| rowspan="3" \|Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]]		\|3\|\|LK3\|\| rowspan="3" \|Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]]
	~~see~~ [[LK-selectable Brand Names]] for details		See [[LK-selectable Brand Names]] for details
	\|\|Purpose unknown (set to "1")		\|\|Purpose unknown (set to "1")
	\|-		\|-

2025-03-30T12:40:40Z

PPI Port C

← Older revision		Revision as of 12:40, 30 March 2025
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	\|-		\|-
	\|3\|\|rowspan=4\|Keyboard line\|\|rowspan=4\|Select keyboard line to be scanned (0-15)		\|3\|\|rowspan=4\|Keyboard line\|\|rowspan=4\|Select keyboard line to be scanned (0-15)
			See [[Programming:Keyboard scanning]] for details
	\|-		\|-
	\|2		\|2

2025-03-30T12:34:05Z

The 8255 in the CPC

← Older revision		Revision as of 12:34, 30 March 2025
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	The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.		The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.

	In these systems it is connected to the [[PSG\|AY-3-8912 Programmable Sound Generator (PSG)]], keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.		In these systems it is connected to the [[PSG\|AY-3-8912 Programmable Sound Generator (PSG)]], keyboard, cassette recorder, the VSYNC of the [[CRTC\|6845 CRTC]] and the "busy" signal from the parallel port.

	The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:		The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:

2025-03-30T12:33:21Z

The 8255 in the CPC

← Older revision		Revision as of 12:33, 30 March 2025
Line 16:		Line 16:
	The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.		The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.

	In these systems it is connected to the AY-3-8912 ~~[[PSG\|~~Programmable Sound Generator (PSG)]], keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.		In these systems it is connected to the [[PSG\|AY-3-8912 Programmable Sound Generator (PSG)]], keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.

	The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:		The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:

2025-03-30T12:32:46Z

The 8255 in the CPC

← Older revision		Revision as of 12:32, 30 March 2025
Line 16:		Line 16:
	The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.		The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.

	In these systems it is connected to the AY-3-8912 Programmable Sound Generator (PSG), keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.		In these systems it is connected to the AY-3-8912 [[PSG\|Programmable Sound Generator (PSG)]], keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.

	The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:		The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:

2025-03-30T12:31:54Z

PPI Port C

2025-03-30T12:30:26Z

PPI Port B

← Older revision		Revision as of 12:30, 30 March 2025
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	!Description		!Description
	!Usage in CPC		!Usage in CPC
	!Usage in KC Compact		!Usage in [[KC Compact]]
	\|-		\|-
	\|7\|\|CAS.IN\|\|Cassette data input\|\|Same as on CPC		\|7\|\|CAS.IN\|\|Cassette data input\|\|Same as on CPC

2025-03-30T12:28:41Z

PPI Port C

← Older revision		Revision as of 12:28, 30 March 2025
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	!Usage		!Usage
	\|-		\|-
	\|7\|\|PSG BDIR\|\|PSG function selection		\|7\|\|PSG BDIR (Bus DIRection)\|\|rowspan=2\|PSG function selection
	\|-		\|-
	\|6\|\|PSG BC1\|\|		\|6\|\|PSG BC1 (Bus Control 1)
	\|-		\|-
	\|5\|\|Cassette Write data\|\|Cassette Out (sometimes also used as Printer Bit7, see [[8bit Printer Ports]])		\|5\|\|Cassette Write data\|\|Cassette Out (sometimes also used as Printer Bit7, see [[8bit Printer Ports]])

2025-03-30T12:18:39Z

PPI Port B

@@ Line 91: / Line 91: @@
 |4||LK4||Screen Refresh Rate ("1"=50Hz, "0"=60Hz)||Set to "1"=50Hz (but ignored by the KC BIOS, which always uses 50Hz even if LK4 is changed)
 |-
-|3||LK3|| rowspan="3" |3bit Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]], see [[LK-selectable Brand Names]] for details.||Purpose unknown (set to "1")
+|3||LK3|| rowspan="3" |Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]]
 |-
 |2||LK2||Purpose unknown (set to "0")
@@ Line 99: / Line 101: @@
 |0||[[CRTC]] VSYNC||Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive)||Same as on CPC
 |-
 |}

2025-03-30T06:21:39Z

PPI Port C