8253 chip - Revision history

MacDeath at 23:41, 16 December 2010

2010-12-16T23:41:26Z

← Older revision		Revision as of 23:41, 16 December 2010
Line 118:		Line 118:
	* [[Media:8253.pdf]] - 8253 Datasheet (slower clock, write-only control registers)		* [[Media:8253.pdf]] - 8253 Datasheet (slower clock, write-only control registers)
	* [[Media:8254.pdf]] - 8254 Datasheet (faster clock, read/write-able control registers)		* [[Media:8254.pdf]] - 8254 Datasheet (faster clock, read/write-able control registers)

			[[Category:Electronic Component]]

Nocash at 13:45, 30 September 2010

2010-09-30T13:45:31Z

@@ Line 4: / Line 4: @@
 and 8254 are basically the same: both are pin-compatible and software compatible. The difference is that the 8254 supports higher clock frequencies, and it includes a readback feature for the control registers (which are write-only on 8253).
 == Usage in CPC interfaces ==
@@ Line 70: / Line 113: @@
    F9DBh Magic Sound Board - 1st 8254 - Timer 0-2 Control          (W)
    Clock source for all six timers is (inverted) 4MHz from expansion port.
 == Datasheets ==

Nocash: /* KDS Serial Interface */

2010-09-30T13:43:56Z

KDS Serial Interface

@@ Line 23: / Line 23: @@
    FBDFh - MHT RS232 8253 timer 0-2 control
    Clock Input is '''unknown''', Clock output goes to a [[8251 USART chip]],
    Clock Output may be further divided by 1, 16, or 64 in the USART chip

Nocash: /* Amstrad Serial Interface */

2010-09-03T22:44:10Z

Amstrad Serial Interface

← Older revision		Revision as of 22:44, 3 September 2010
Line 15:		Line 15:
	Clock Input seems to be 2MHz, Clock output goes to a [[Z80-DART/Z80-SIO chip]],		Clock Input seems to be 2MHz, Clock output goes to a [[Z80-DART/Z80-SIO chip]],
	Clock Output may be further divided by 1, 16, 32, or 64 in the DART chip		Clock Output may be further divided by 1, 16, 32, or 64 in the DART chip

			=== MHT Ingenieros RS232 para Amstrad ===
			Used by [[RS-232 para Amstrad]] from MHT Ingenieros, mapped to Ports:
			FBDCh - MHT RS232 8253 timer 0 (transmit baudrate)
			FBDDh - MHT RS232 8253 timer 1 (receive baudrate)
			FBDEh - MHT RS232 8253 timer 2 (used as 1ms timer)
			FBDFh - MHT RS232 8253 timer 0-2 control
			Clock Input is '''unknown''', Clock output goes to a [[8251 USART chip]],
			Clock Output may be further divided by 1, 16, or 64 in the USART chip

	=== KDS Serial Interface ===		=== KDS Serial Interface ===

Nocash: /* Aleste 520EX Serial Interface and Color Palette Swap */

2010-02-28T10:24:03Z

Aleste 520EX Serial Interface and Color Palette Swap

← Older revision		Revision as of 10:24, 28 February 2010
Line 27:		Line 27:
	=== Aleste 520EX Serial Interface and Color Palette Swap ===		=== Aleste 520EX Serial Interface and Color Palette Swap ===
	Also used by [[Aleste 520EX]] CPC clone:		Also used by [[Aleste 520EX]] CPC clone:
	~~F4X0h Aleste~~ PPI Port A, 8253 Baudrate Timer 0 (RX Clock) (W)		FABCh ExtPort: Forward PPI Port A to 8253 Baudrate Timer 0 (RX Clock) (W)
	~~F4X1h Aleste~~ PPI Port A, 8253 Baudrate Timer 1 (TX Clock) (W)		FABDh ExtPort: Forward PPI Port A to 8253 Baudrate Timer 1 (TX Clock) (W)
	~~F4X2h Aleste~~ PPI Port A, 8253 ColorSet Timer 2 (FUTURE) (W)		FABEh ExtPort: Forward PPI Port A to 8253 ColorSet Timer 2 (FUTURE) (W)
	~~F4X3h Aleste~~ PPI Port A, 8253 Timer 0-2 Control Registers (W)		FABFh ExtPort: Forward PPI Port A to 8253 Timer 0-2 Control Registers (W)
	~~Ahhhhhhhhh, actually, above should be Port FABxh rather than F4Xxh !!! (?) Ie. first write data to F4XXh, then issue write to FABxh (with /CS and A0,A1~~)
	Clock Input for RX/TX is 4MHz, Clock output goes to a [[8251 USART chip]],		Clock Input for RX/TX is 4MHz, Clock output goes to a [[8251 USART chip]],
	Clock Output may be further divided by 1, 16, or 64 in the 8251 chip,		Clock Output may be further divided by 1, 16, or 64 in the 8251 chip,
Line 37:		Line 36:
	the FUTURE clock is restarted via GATE=[[CRTC]]'s "CURSOR" output,		the FUTURE clock is restarted via GATE=[[CRTC]]'s "CURSOR" output,
	All registers are write-only (the 8251 chips /RD is wired to VCC)		All registers are write-only (the 8251 chips /RD is wired to VCC)
	PPI Port A ~~data direction must be~~ output,		* Usage: Set PPI Port A to output. Write Data to PPI Port A (F4XXh), then set/clear the CS53 bit with two writes to Port (FABCh+n), where n is the 8253 register index.
	~~Aleste ExtReg must enable access~~ to 8253~~, and disable access to PSG~~
	* Note: According to the Aleste schematic, clock input is 4MHZ (16MHZ/4), and it uses a russian 8253 clone. Not sure if that is correct...? Theoretically the 8253 supports only max 2.6MHZ, and anything faster requires a 8254, not a 8253.		* Note: According to the Aleste schematic, clock input is 4MHZ (16MHZ/4), and it uses a russian 8253 clone. Not sure if that is correct...? Theoretically the 8253 supports only max 2.6MHZ, and anything faster requires a 8254, not a 8253.

Nocash: /* Aleste 520EX Serial Interface and Color Palette Swap */

2010-02-28T09:58:56Z

Aleste 520EX Serial Interface and Color Palette Swap

← Older revision		Revision as of 09:58, 28 February 2010
Line 31:		Line 31:
	F4X2h Aleste PPI Port A, 8253 ColorSet Timer 2 (FUTURE) (W)		F4X2h Aleste PPI Port A, 8253 ColorSet Timer 2 (FUTURE) (W)
	F4X3h Aleste PPI Port A, 8253 Timer 0-2 Control Registers (W)		F4X3h Aleste PPI Port A, 8253 Timer 0-2 Control Registers (W)
			Ahhhhhhhhh, actually, above should be Port FABxh rather than F4Xxh !!! (?) Ie. first write data to F4XXh, then issue write to FABxh (with /CS and A0,A1)
	Clock Input for RX/TX is 4MHz, Clock output goes to a [[8251 USART chip]],		Clock Input for RX/TX is 4MHz, Clock output goes to a [[8251 USART chip]],
	Clock Output may be further divided by 1, 16, or 64 in the 8251 chip,		Clock Output may be further divided by 1, 16, or 64 in the 8251 chip,

Nocash: /* Magic Sound Board for Aleste 520EX */

2010-02-22T18:33:25Z

Magic Sound Board for Aleste 520EX

← Older revision		Revision as of 18:33, 22 February 2010
Line 51:		Line 51:
	F9DAh Magic Sound Board - 1st 8254 - Timer 2 (DMA Channel 2) (W)		F9DAh Magic Sound Board - 1st 8254 - Timer 2 (DMA Channel 2) (W)
	F9DBh Magic Sound Board - 1st 8254 - Timer 0-2 Control (W)		F9DBh Magic Sound Board - 1st 8254 - Timer 0-2 Control (W)
			Clock source for all six timers is (inverted) 4MHz from expansion port.

	== Timer Registers ==		== Timer Registers ==

Nocash: /* Control Registers */

2010-02-22T18:20:59Z

Control Registers

← Older revision		Revision as of 18:20, 22 February 2010
Line 75:		Line 75:
	== Control Registers ==		== Control Registers ==

	8253 Timer 0-2 Control Registers (W)		* 8253/8254 Timer 0-2 Control Registers (W)
	This port allows to configure three write-only 6bit registers: Bit6-7 specify which of the registers is to be updated, Bit0-5 contain the new value for that register.		This port allows to configure three write-only 6bit registers: Bit6-7 specify which of the registers is to be updated, Bit0-5 contain the new value for that register.

	7-6 Counter Number (0..2=Counter 0..2, 3=Reserved)		7-6 Counter Number (0..2=Counter 0..2, and 8253: 3=Reserved, or 8254: 3=Readback)
	5-4 Read/Load (0=Latching?, 1=LSB only, 2=MSB only, 3=LSB-then-MSB)		5-4 Read/Load (0=Latching?, 1=LSB only, 2=MSB only, 3=LSB-then-MSB)
	3-1 Mode		3-1 Mode

Nocash: /* Timer Registers */

2010-02-22T18:19:13Z

Timer Registers

← Older revision		Revision as of 18:19, 22 February 2010
Line 54:		Line 54:
	== Timer Registers ==		== Timer Registers ==

	8253 Timer 0 Register (R/W)		* 8253/8254 Timer 0 Register (R/W)
	8253 Timer 1 Register (R/W)		* 8253/8254 Timer 1 Register (R/W)
	8253 Timer 2 Register (R/W)		* 8253/8254 Timer 2 Register (R/W)
	These ports allow to access three decrementing 16bit timers. Assuming that the corresponding Control Registers are set to "LSB-then-MSB", the 16bit reload values (aka divider values) are written in two 8bit fractions:		These ports allow to access three decrementing 16bit timers. Assuming that the corresponding Control Registers are set to "LSB-then-MSB", the 16bit reload values (aka divider values) are written in two 8bit fractions:

Nocash: /* Control Registers */

2010-02-22T18:18:13Z

Control Registers

← Older revision		Revision as of 18:18, 22 February 2010
Line 79:		Line 79:

	7-6 Counter Number (0..2=Counter 0..2, 3=Reserved)		7-6 Counter Number (0..2=Counter 0..2, 3=Reserved)
	5-4 Read/Load (0=Latching?, 1=~~MSB~~ only, 2=~~LSB~~ only, 3=LSB-then-MSB)		5-4 Read/Load (0=Latching?, 1=LSB only, 2=MSB only, 3=LSB-then-MSB)
	3-1 Mode		3-1 Mode
	0=Interrupt on Terminal Count		0=Interrupt on Terminal Count